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| sajattack[m] | got me a cle-215+ 😀 | 00:25 |
|---|---|---|
| sajattack[m] | I think I got it j-tagging, now I'm trying to install vivado | 00:29 |
| sajattack[m] | it looks like it's failing a device id check, is that normal? | 00:31 |
| sajattack[m] | https://hatebin.com/mqrgajnjfp | 00:31 |
| tpb | Title: hatebin (at hatebin.com) | 00:31 |
| sajattack[m] | * it looks like openocd is failing a device id check, is that normal? | 00:33 |
| sajattack[m] | https://hatebin.com/mqrgajnjfp | 00:33 |
| tpb | Title: hatebin (at hatebin.com) | 00:33 |
| sajattack[m] | oops, forgot this was irc and that would send twice rather than edit | 00:33 |
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| sajattack[m] | https://twitter.com/sajattack/status/1372000674519547905 | 01:48 |
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| sajattack[m] | has anyone flashed the cle-215 with a jlink that could give me a hand? | 05:06 |
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| sajattack[m] | I think my openocd version and my jlink fw version are out of sync | 06:10 |
| sajattack[m] | but both are latest :/ | 06:10 |
| zyp | I'd suspect you got the pinout wrong | 06:41 |
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| sajattack[m] | I don't think so, in my hatebin link it's communicating enough to read a device id, but openocd is giving a libusb error when I try to flash | 06:49 |
| sajattack[m] | despite running as root and everything | 06:50 |
| zyp | looks to me like it's trying to read the device id and just getting garbage back | 06:51 |
| sajattack[m] | maybe | 06:51 |
| zyp | which I guess is how it'd look if you swapped JTMS and JTDI | 06:51 |
| RaivisR__ | also, 25MHz and breadboard? | 06:52 |
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| zyp | says reduced to 4 MHz | 06:52 |
| zyp | but yeah, might be worth reducing that too | 06:52 |
| RaivisR | ah, yes, let me introduce myself, got ecp5 vip, trying to put litex on it | 06:52 |
| RaivisR | or rather did it yesterday already, today adding dram, peripherals and putting linux on it | 06:53 |
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| sajattack[m] | wiring looks right to me, lowered the clock, same behaviour | 07:12 |
| sajattack[m] | even tried swapping tdi and tms | 07:13 |
| sajattack[m] | whoa it found a xilinx device id | 07:19 |
| sajattack[m] | magic | 07:19 |
| sajattack[m] | grounds were fucked | 07:19 |
| sajattack[m] | still having libusb errors but led turned solid | 07:20 |
| sajattack[m] | but I guess I need a uart cable to check further? | 07:23 |
| RaivisR | to see litex bootloader prompt? i am n00b at this but yes, i had only clock, reset and serial in platform definition and it showed me boobloader prompt | 07:42 |
| RaivisR | *bootloader | 07:45 |
| RaivisR | of course :) | 07:45 |
| sajattack[m] | https://hatebin.com/dhvcfplakh | 07:55 |
| tpb | Title: hatebin (at hatebin.com) | 07:55 |
| sajattack[m] | this is the part that seems like bad jlink firmware | 07:55 |
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| zyp | sajattack[m], you can use the crossover uart over pcie | 08:15 |
| zyp | but first you'll want to make sure the new gateware enumerated over pcie | 08:16 |
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| sajattack[m] | Ah yes, lspci, should have thought of that | 08:18 |
| keesj | Hi, I back... :P I want to do a small project with tinyfpga_bx and a soft core. | 08:36 |
| keesj | it looks like this should be almost trivial at there is already a board file and I just copyed the .py file and would like to get to hello world | 08:37 |
| keesj | I hope to get to a state like here https://github.com/kekiefer/tinyfpga-litex e.g. have my own "bios" and be able to start adding IP | 08:38 |
| keesj | even nicer if this can be combined with and USB serial .. but that probably won't fit | 08:41 |
| keesj | so in the link I posted above the code is compiled to xip and only the minimal sram is used. this setup is different from the commited code | 09:42 |
| zyp | you might want to look at how the fomu does usb with litex | 09:56 |
| keesj | thanks for the tip | 10:12 |
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| keesj | I was messing around with the firmware section but I think the ROM/BIOS it not functioning | 12:04 |
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| RaivisR_ | aparently just throwing all the pins at litedram does not quite work, oh well, more digging | 14:34 |
| rozpruwacz | _florent_: did You get my message i'v sent yesterday around 3pm utc ? I disconnected from the irc and may lost your reply. | 15:02 |
| RaivisR_ | single chip works, now to figure how to make them both work | 15:07 |
| keesj | I am looking at nand flash (single data rate) and would like to read out some data from it. When i look at the timing diagrams (the data in no clocked) there is a varatity of different setup and hold times e.g. https://i.imgur.com/3FgJSvH.png is there a nice way to handle this "complex" set of changes ? I am currently doing a clock divider and a state machine | 15:08 |
| RaivisR_ | i stand corrected - worked on first boot | 15:09 |
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| keesj | I did have a look a glawgow code that is supposed to understand parallel nand but I don't have the board | 15:10 |
| keesj | RaivisR_: nice | 15:10 |
| RaivisR_ | well, not quite my definition of nice, but yes, at least something works for some time :) | 15:12 |
| keesj | sometimes.... I am quite happy when something just works (for some time0 | 15:17 |
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| _florent_ | rozpruwacz: sorry, I got the message yes but haven't been able to look at it yet | 16:24 |
| _florent_ | RaivisR_: which board are you testing? | 16:25 |
| _florent_ | RaivisR_: can you share the BIOS log if failing? | 16:25 |
| RaivisR_ | i am learning, on ecp5 vip, it is more of me being total noob than anything else | 16:26 |
| RaivisR_ | i am rolling my own platform file as I go | 16:26 |
| _florent_ | ok, for the initial tests, I would recommend using the same sys_clk_freq than the Versa ECP5 | 16:28 |
| RaivisR_ | versa has single sdram chip, this one has two | 16:29 |
| _florent_ | What's the behaviour when you say "something works for some time"? | 16:29 |
| rozpruwacz | _florent_: sure, no problem :) | 16:31 |
| RaivisR_ | if I define pins for only one chip, initial memory test passes, on consecutive runs it fails, but I am sure it is me doing something wrong, i am just talking to myself loud (silently hoping that maybe someone will yell - i know that one!) :) | 16:31 |
| _florent_ | RaivisR_: OK, testing only one chip initially is a good idea, you could switch to the two chips when stable with one :) | 16:36 |
| RaivisR_ | I´ll go all in :) digging through sources and trying understand what is what and why helps to soak in the feel original dev had when writing the whole thing | 16:37 |
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| RaivisR | making progress, bus and addr errors both 0, data errors a lot | 16:39 |
| RaivisR | if I have 4GiB address space and 2GiB sdram, I probably should think about where do I put it | 16:44 |
| somlo | _florent_: is there an easy way to capture a module's FSM state as one of the entries in `analyzer_signals` ? | 17:07 |
| _florent_ | somlo: yes, you can just add the FSM to the list of things you want ot observe, it will finalize it and add the state signal to the analyzer: https://github.com/enjoy-digital/litescope/blob/master/litescope/core.py#L277-L280 | 17:09 |
| somlo | oh cool, I'm going to redo my capture to include the FSM state info, that should make it a bit easier to tell what's happening and *when* | 17:10 |
| _florent_ | somlo: great, thanks | 17:31 |
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| keesj | I think .. implemeing a latch module might be a nice solution to my problem | 18:31 |
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