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| pftbest | zyp: i have the same exact problem! please ping me if you find how to fix this | 00:29 |
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| Melkhior | _florent_ For the Arrow Deca board I've tried to put the pinouts from the documentation in a Platform file (completely untested!): https://github.com/rdolbeau/litex-boards/blob/deca/litex_boards/platforms/arrow_deca.py | 09:37 |
| _florent_ | Melkhior: nice, thanks. A first version by hansfbaier has already been merged in litex_boards, both are probably complementary, we should try to merge them | 10:16 |
| Melkhior | darn didn't notice :-) | 10:16 |
| Melkhior | copy/pasting from the documentation is the one thing I can do ;-) | 10:17 |
| _florent_ | :) It will probably still be useful and can help catching errors | 10:18 |
| Melkhior | anyway getting the board at $37 was a good move, as they're now listed as 'quote' :-( | 10:18 |
| _florent_ | indeed, I also received mine BTW | 10:19 |
| Melkhior | excellent :-) | 10:20 |
| Melkhior | I also see a targets for deca, is it usable yet ? Though the question is more 'what can you do with LiteX when there's no external memory' I suppose ; i've only ever tried Linux but there's probably some use case that can run out of the FGPA on-board memory I guess. | 10:22 |
| zyp | _florent_, any suggestions for how to troubleshoot etherbone? I'm running the ecpix5 example from litex-boards, slightly modified to call add_etherbone() instead of add_ethernet(), but it's not responding to ARP and it's also not responding to ICMP when manually inserting an entry into the ARP table | 10:35 |
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| shorne_ | Hello, On my arty board I switched on etherbone to try to use litescope | 12:05 |
| shorne_ | However, as expected, the netbooting no longers works | 12:05 |
| shorne_ | I tried to boot from sdcard and for somereason it hangs after trying to read boot.json | 12:06 |
| shorne_ | I am probably having issues partitioning/formatting the sdcard correctly | 12:06 |
| shorne_ | any suggestions on alternative boot methods? Is there a way to load an image over etherbone? I could write a program to do it, but i assume somethign already exists | 12:07 |
| shorne_ | trying litex_term now | 12:10 |
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| Melkhior | Hello, | 13:06 |
| Melkhior | So I got a bitstream for the MAX10, and it seems OK (including programming) as I see the LEDs do their thing. | 13:06 |
| Melkhior | But I don't know how to see if there's anything on the serial port, as in the target file it's defined as 'jtag atlantic' and I don't know what that is. | 13:06 |
| Melkhior | I seem to have a 'new' tty that showed up when I plugged the USB cable for the usb blaster, but it doesn't display anything in minicom at 115200 or 1000000 | 13:06 |
| Melkhior | Any suggestion ? Or maybe I shouldn't expect anything on the TTY as there's no memory for the BIOS code to run in ? | 13:06 |
| Melkhior | (that's the MAX10 on the Deca board) | 13:07 |
| Melkhior | I see lxterm has a --jtag-name that can take 'jtag_atlantic' as an option, but not sure what 'device' to give it | 13:25 |
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| Melkhior | Well, didn't figure it out so I just replaced the 'jtag_atlantic' thing by a 'normal' liteuart on a couple of pins in the P8 header (in {targets,platforms}/deca.py) and it worked perfectly :-) | 14:20 |
| Melkhior | --=============== SoC ==================-- | 14:20 |
| Melkhior | CPU: VexRiscv @ 50MHz | 14:20 |
| Melkhior | BUS: WISHBONE 32-bit @ 4GiB | 14:20 |
| Melkhior | CSR: 32-bit data | 14:20 |
| Melkhior | ROM: 32KiB | 14:20 |
| Melkhior | SRAM: 8KiB | 14:20 |
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| zyp | _florent_, is it still not possible to run etherbone with dw>8? | 15:02 |
| zyp | I found out it works if I up the sysclk to 125MHz (except then I have problems meeting timing), but upping the dw to LiteEthIPCore doesn't seem to work | 15:04 |
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| _florent_ | shorne_: It's possible to do a serialboot over Etherbone, but that's not really fast (so could be an issue in your case with Linux images). If you want to try, you can use --uart_name=crossover --with-etherbone on the arty target. | 17:40 |
| _florent_ | then litex_server --udp | 17:40 |
| _florent_ | and litex_term bridge | 17:40 |
| _florent_ | Another option is to use the Hybrid Ethernet Mac Mode that provides both Ethernet and Etherbone on a different IP address. | 17:41 |
| _florent_ | But this is not yet properly integrated in LiteX, so you have to use code similar to this; | 17:41 |
| _florent_ | https://www.irccloud.com/pastebin/2zk3vbE0/ | 17:42 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 17:42 |
| _florent_ | Another option could be to use LiteScope over JTAG | 17:43 |
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| _florent_ | you would just need to add this to your target: | 17:44 |
| _florent_ | self.add_jtagbone() | 17:44 |
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| _florent_ | then litex_server jtag --jtag-config=openocd_xc7_ft2232.cfg | 17:45 |
| _florent_ | You can find more info here: https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC#add-a-jtag-bridge-to-your-soc | 17:45 |
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| _florent_ | This is probably the option that requires the minimal changes | 17:45 |
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| _florent_ | Melkhior: For the deca, I tested hansfbaier's initial port with litex_term jtag --jtag-name=jtag_atlantic | 17:47 |
| _florent_ | But you can also juste use nios2terminal | 17:47 |
| _florent_ | juste/just | 17:48 |
| _florent_ | zyp: That's already good you got it working at 125MHz, I remember being able to also use a 50MHz clock with Etherbone on the Colorlight | 17:50 |
| _florent_ | zyp: This would need to be investigated more | 17:50 |
| Melkhior | _florent_ Thanks. Didn't know about nios2terminal. My workaround w/ litex' own uart worked for me:-) Now if only there was a memory controller for the DDR3;-) (someone in eevblog's forum is building one with the Deca as a target, but no idea if the interface will be easy to integrate in Litex...) | 17:50 |
| _florent_ | zyp: Eventually with LiteScope | 17:50 |
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| _florent_ | Melkhior: Integrating the Altera controller should not be to complicated, I already did that in the past, It would just need a Wishbone/AXI bridge (it's even possible it will already be AXI capable, which would simplify the work). | 17:53 |
| _florent_ | Melkhior: Ideally, it would be nice to add a proper PHY in LiteDRAM, but this could be an intermediate solution | 17:54 |
| zyp | _florent_, I've been digging into it and fixed a couple of small things, but I'm still not having any luck with giving LiteEthUDPIPCore dw=16 even at 125MHz | 18:00 |
| _florent_ | zyp: not sure 16 has been tested but 8 and 32 have been | 18:08 |
| zyp | I tried that too | 18:08 |
| zyp | yeah, tried it again, still no ARP | 18:11 |
| _florent_ | zyp: ok, I really think this is related to the PHY or reset sequence. That would be interesting to add LiteScope on the PHY source/sink and compare with frames on the Host with Wireshark | 18:16 |
| zyp | how do you figure? phy.dw is hardcoded to 8 so the phy behavior shouldn't differ even if the MAC is set to a different dw | 18:19 |
| zyp | I see the width conversion happen in the pipelines in LiteEthMACCore | 18:20 |
| _florent_ | I really think this is a low level issue and suspect the packet is already malformed at the phy.source. At least that would be the first thing I would look at, and then add the other source of the stack, up to to the ARP, and then go in the other direction for the returned packet. | 18:22 |
| _florent_ | This way, on an isolated network, you can just trigger on phy.source and see all the layers at once | 18:23 |
| zyp | I was hoping to avoid having to set up another wishbone bridge to be able to use litescope :) | 18:24 |
| zyp | I just think that since it works for dw=8, the issue should be somewhere above the StrideConverter | 18:26 |
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| _florent_ | zyp: that's a good hypothesis, but a design not correctly constrainted or incorrect reset sequence can also produce strange behavior. I'll try also have a look at this tomorrow, that would be nice to have the Etherbone and the hardware UDP/IP working on the ECPIX5 | 19:25 |
| zyp | hmm, litescope is not getting a trigger on arp.rx.sink.valid | 20:04 |
| pftbest | zyp: does your ethcore.mac.core.preamble_errors.status increase for each incoming packet? I get a strange behavior that with one of my routers this number increase for each packet consistently, but it stays 0 with the other router. | 20:15 |
| pftbest | doesn't work on both of them though, so it's probably not related | 20:15 |
| pftbest | just a curious thing i noticed | 20:17 |
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| zyp | tools are not super cooperative today and since I'm not getting a trigger on arp.rx.sink.valid, I'm instead looking at some random udp broadcast packet it picked up, and as far as I can see the mac output looks sane with dw=32 | 20:31 |
| shorne_ | _florent_: thanks, I will try some of those options | 20:40 |
| zyp | ah, here we go, it appears to be an endianness problem | 20:52 |
| zyp | https://bin.jvnv.net/file/ZJLY6.png | 20:57 |
| zyp | ethertype should be 0800, not 0045 :) | 20:57 |
| zyp | setting endianness=little when instancing LiteEthMAC in LiteEthIPCore appears to help: https://bin.jvnv.net/file/hADdh.png | 21:46 |
| zyp | now it also replies to pings | 21:46 |
| shorne_ | _florent_: I got it working over jtag thanks, I will send a PR to add to arty.py | 21:50 |
| zyp | etherbone still doesn't appear to work, and flipping endianness in LiteEthEtherboneRecord doesn't appear to help either | 22:48 |
| zyp | and it's too late to do more on this tonight | 22:49 |
| zyp | but just getting arp/icmp working is decent progress :) | 22:49 |
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