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| promach3 | For DDR memory, do I really need tdqs and odt ? Another question is do I need twr for write_AP ? By the way, I had done an initial code for the DDR3 memory controller in verilog :: https://gist.github.com/promach/2c477b1dbc39f04a1271fb229e6d678c | 23:10 |
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| * promach3 uploaded an image: image.png (70KiB) < https://matrix.org/_matrix/media/r0/download/matrix.org/cTJqalHjvFRewFHLqGMBtRDf/image.png > | 23:43 | |
| promach3 | I am confused with how `TDQS` and `TDQS#` pins be driven ? I suppose these two pins are of `inout` nature | 23:44 |
| * promach3 uploaded an image: image.png (59KiB) < https://matrix.org/_matrix/media/r0/download/matrix.org/egQMkdusvxTSvqcdzbYejcWa/image.png > | 23:47 | |
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