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| cr1901_modern | _florent_: Was this a typo? https://github.com/enjoy-digital/litex/commit/b9e0c95c1836f685386a6f24004882a52c98a120#diff-073894f16fcec5dcb0b5d79a975b59f45ce25b696436bee32a6be0ab8344b960L169 Because it triggers an assertion failure | 05:44 |
|---|---|---|
| cr1901_modern | https://github.com/antonblanchard/microwatt/blob/master/xics.vhdl#L309 | 05:44 |
| cr1901_modern | Getting this core running at all has been quite frustrating | 05:45 |
| cr1901_modern | Okay I can't build microwatt w/ the FOSS tools. The autoname pass brings my Linux machine to its knees w/ 7GB of RAM usage (wtaf?!) | 05:56 |
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| cr1901_modern | https://twitter.com/cr1901/status/1363373598354907137 I am stumped by this, tbh. Would appreciate any insight from anyone who has compiled a litex SoC using microwatt w/ the free tools | 06:23 |
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| _florent_ | cr1901_modern: Hi, IIRC there was an with Microwatt and the FOSS tools (not sure it has been fixed), you had reduce the I/D Cache: | 09:17 |
| _florent_ | https://github.com/antonblanchard/microwatt/blob/master/core.vhdl#L220 | 09:17 |
| _florent_ | https://github.com/antonblanchard/microwatt/blob/master/core.vhdl#L402 | 09:17 |
| _florent_ | IIRC I was setting it to 2 | 09:17 |
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| cr1901_modern | _florent_: I'll take a look. What about this line? https://github.com/antonblanchard/microwatt/blob/master/xics.vhdl#L309 | 11:25 |
| cr1901_modern | I had to comment out this assert manually, because litex wants 256 interrupt lines | 11:26 |
| cr1901_modern | Did you have a modified microwatt repo you were testing against? | 11:26 |
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| _florent_ | cr1901_modern: not sure about xics, I just know we are using a specific commit of pythondata-cpu-microwatt since things were moving fast in the microwatt repo | 12:18 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex_setup.py#L56 | 12:18 |
| cr1901_modern | The commit in question has the same assert: https://github.com/litex-hub/pythondata-cpu-microwatt/blob/f9807b6de50aab8b264f0bc9a945e42f1a636456/pythondata_cpu_microwatt/vhdl/xics.vhdl#L309 | 12:21 |
| cr1901_modern | Anyways, would you be willing to run the following command at the root of litex-boards? | 12:22 |
| cr1901_modern | python3 litex_boards/targets/orangecrab.py --cpu-type=microwatt --cpu-variant=standard+ghdl+irq --integrated-rom-size=40960 --no-compile-gateware --no-compile-software | 12:22 |
| cr1901_modern | And tell me if it fails or not? | 12:23 |
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| _florent_ | cr1901_modern: I'll be able to run it tomorrow yes | 17:19 |
| cr1901_modern | Alright, tyvm. Taking a break from microwatt for the time being lol | 17:20 |
| _florent_ | (don't have access to my dev computer now) | 17:20 |
| cr1901_modern | >(4:17:38 AM) _florent_: IIRC I was setting it to 2 | 17:23 |
| cr1901_modern | 2 lines, or 2 words per line | 17:23 |
| cr1901_modern | (Seems to make more sense to do 2 words per line) | 17:24 |
| cr1901_modern | Anyways, looking at the repo, the autoname issue has come up before, but I still may make an issue | 17:24 |
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| nickoe | What editor are you using for litex python scripts? | 20:52 |
| zyp | «you» as in anybody? I use vscode, as for anything else these days | 21:27 |
| nickoe | zyp: yes | 21:35 |
| nickoe | anyone. | 21:35 |
| nickoe | Ok, I am currently using pycharm, but it is not happy about jumping around the code for things like: dma = LiteDRAMDMAReader() ... dma.source it can find, but not dma.source.data as for example used in https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/bist.py#L509 | 21:37 |
| zyp | with a dynamic language like python, there's limits to what you can reasonably expect your editor to know about | 21:38 |
| nickoe | yeah | 21:39 |
| nickoe | I understand that. | 21:39 |
| nickoe | Just a bit annoying when you are learning the codebase. | 21:39 |
| zyp | I guess you could run the code in a debugger, set a breakpoint at what you're working, and inspect the actual objects that exist :) | 21:40 |
| nickoe | yeah | 21:41 |
| nickoe | that works at least. | 21:42 |
| nickoe | Anyway, I am trying to dump that memory region from ram to some output pins / registers. So readin the bist.py stuff, https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/bist.py#L134 there is a mention of awidth and ashift. For the native interface they are ashift = 4 and awidth 28. | 21:43 |
| nickoe | How should I understand that? Is that because four bytes are read for each word read? | 21:44 |
| zyp | sounds like 16 to me | 21:45 |
| nickoe | I don't understand why the awidth is not just 32. | 21:46 |
| zyp | 2**4 is 16, and if you've got a 32-bit address accessing a 16-byte word then the lower four bits in the address will be all zeroes, so you can shift it by 4 and only keep the upper 28 bits of the address | 21:47 |
| zyp | I don't know the details of the particular code you're looking at, but I guess something like this is what is going on | 21:47 |
| zyp | if you have a 32-bit wide data bus, it's common to leave out the bottom two address bits | 21:48 |
| zyp | and in this case it sounds like you've got 128-bit wide data | 21:48 |
| nickoe | mm, ok, I guess that makes sense a the RAM is accessed with 128 bit widths for the data? | 21:48 |
| nickoe | = 16 bytes | 21:49 |
| zyp | that's how it sounds to me | 21:49 |
| zyp | I think that's a result of the dram being accessed in bursts | 21:49 |
| nickoe | "bursts" is that a general term used for SDRAM? | 21:50 |
| zyp | I'm not an expert on SDRAM, but as far as I understand it you can't ask a RAM for only one word, it'll give you a burst of 8 words or something, | 21:51 |
| nickoe | How many sysclk cycles does it take to read that from the RAM? | 21:51 |
| nickoe | zyp: ok, that sounds about right | 21:52 |
| zyp | several, it's part of the reason SDRAM has higher latency :) | 21:52 |
| zyp | I mean, I figure bursts are a throughput optimization | 21:53 |
| nickoe | in thi case it is also ddr3 | 21:53 |
| zyp | if there's a several cycle delay for the memory to locate the data you asked for, it makes sense to return more than just a single word at a time | 21:54 |
| nickoe | yes | 21:54 |
| zyp | but as far as I'm concerned, the details are not all that interesting unless you're writing the memory controller, I just want to use the memory controller :) | 21:55 |
| nickoe | yeah, my goal is also just to _use_ it and not write it. | 21:55 |
| nickoe | How can I buffer my data such that I can push it out at a sysclk rate? | 21:56 |
| zyp | think in terms of streams | 22:00 |
| nickoe | Well, I do want to attempt to stream out data from the ram. I wanted to read it with LiteDRAMDMAReader and then push it in to an AXI Stream Interface. | 22:02 |
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