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| tmbinc | _florent_: https://github.com/litex-hub/litex-boards/pull/176 for further review, this is really just a first iteration | 00:13 |
|---|---|---|
| tmbinc | but it appears to work correctly after ~1 minute of scoping | 00:13 |
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| nickoe | _florent_: How does one normally go about using the RAM memory space in gateware together witH the CPU having access to memory as well? Does the memory have an AXI interface that the CPU uses? Does this mean that gateware can just use AXI as well? | 07:08 |
| nickoe | tmbinc: Is that the siglent scope? | 07:12 |
| zyp | nickoe, is that a litedram question, or are you thinking RAM in general? | 07:18 |
| zyp | the general question is bus interconnects that arbitrates access from multiple masters | 07:19 |
| zyp | general answer* | 07:19 |
| zyp | this can be wishbone or AXI or whatever | 07:19 |
| nickoe | zyp: I am talking in general, but I want to implememt it specifically with litex, so I guess it is a litedram question in gemeral. | 07:20 |
| zyp | litedram has an internal crossbar interconnect so that you can attach multiple masters directly | 07:20 |
| nickoe | My current goal is to stuff some IQ samples in memory. I can do that with the boot.jsom and load it from the SD card. | 07:20 |
| nickoe | Ghen I want to stuff those samples to a DAC at a 100MHz rate if possible somehow. I am still trying to understamd how to arch this sanely. | 07:21 |
| nickoe | After that I would need to add some DSP in gateware (in verilog) to generate those IQ samples. | 07:23 |
| zyp | a typical litex system will have a main wishbone interconnect across the various slaves, including litedram, and then if you've got a high performance cpu it might also be plugged directly into the litedram so it can bypass the main interconnect when accessing the main ram | 07:24 |
| zyp | so if you wanna do some sort of DMA, you can either make something that plugs into the main interconnect and can access the whole system memory space, or something that plugs directly into litedram if it only needs access to the main ram | 07:25 |
| zyp | in the latter case, you might want to use one of these adapters: https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/dma.py | 07:26 |
| nickoe | Ok, I think that is what I want, but I have no previous resl experince i using AXI or Wishbone directly, so i am also trying to understand how it can be used. | 07:30 |
| zyp | https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/axi.py or https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/wishbone.py | 07:31 |
| nickoe | Mm, I guess I can somehow connect the data unbuffered to some registers that I map to the output pins of the FPGA that connecto the the DAC, but wouldn't that sufffer from read/access latencies? | 07:39 |
| nickoe | maybe there exist some other SDR implemented with litex that I can look at? | 07:40 |
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| _florent_ | tmbinc: nice you've been able to reuse and integrate your previous offsetdac code! | 09:21 |
| _florent_ | tmbinc: in LiteX-Boards I generally try to only have the base support for hardware (Serial, Ethernet, DRAM, etc...), and add custom peripherals in application projects | 09:22 |
| _florent_ | tmbinc: we could maybe continue developing the scope part in the 360nosc0pe organization? (and have offsetdac code + test code + others custom peripherals there) | 09:24 |
| _florent_ | nickoe: the default LiteX SoC are using a single DRAM port that is mapped on the main bus of the SoC (Wishbone or AXI) | 09:27 |
| _florent_ | nickoe: this is convenient for CPU accesses but the main bus can be a bottleneck | 09:27 |
| _florent_ | nickoe: so it's also possible to create direct ports to the DRAM too, with get_port of the crossbar: https://github.com/enjoy-digital/litedram/blob/master/litedram/core/crossbar.py#L79 | 09:28 |
| _florent_ | nickoe: this will provide you a native LiteDRAM interface, that you can then convert to Wishbone/AXI if more convenient | 09:29 |
| _florent_ | nickoe: the BIST module is for example creating two additional ports (one for write, one for read) and use them to stress the DRAM: | 09:31 |
| _florent_ | https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/bist.py | 09:31 |
| _florent_ | integrated with: | 09:31 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1230-L1235 | 09:31 |
| shorne | somlo: thanks, I will look at these issues too then. This is blocking me using the mmc card as swap to run the glibc test. It works but way too slow and the linux start killing things | 09:37 |
| acathla | _florent_, your patch : moving the ibus out of main wishbone bus to an Arbiter (or interconnectShared) to ROM (and RAM) worked well. But adding an icache to the vexriscv give me almost the same results for a bit less LC | 10:27 |
| _florent_ | acathla: ah ok, the issue was indeed that access on dbus were preventing instructions to be fetched, the instructions are now in your icache so yes the bypass will be less useful, but I thought it was not possible in your case to add the icache (using too much resources) | 10:51 |
| _florent_ | acathla: even if no longer useful in your case, the things we experimented will probably be useful later | 10:52 |
| _florent_ | acathla: so now you are able to saturate your link with the CPU? | 10:55 |
| acathla | I did the math again, this time the icache (1024) costs 47LC and 4 RAM | 10:56 |
| acathla | _florent_, yes, I also passed everything in 32 bits, so 4 times faster to write to the FIFO (but it costs some LC) | 10:57 |
| acathla | I think there is something overkill with the actual UART, taking too much LC for the iCE40 (but you don't care on bigger FPGAs) | 10:58 |
| acathla | as I said on #tomu : 317 LC for a simple UART, 511LC if it's a master on wishbone | 11:00 |
| _florent_ | acathla: have you tried reducing the FIFO's depth? | 11:02 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L195-L196 | 11:02 |
| _florent_ | (similar to: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L427) | 11:02 |
| _florent_ | also are you using the RS232PHY or just a custom PHY? | 11:02 |
| acathla | _florent_, behaviors is strange, sometimes it only uses RAM so not much LC, sometimes it uses a lot of LC. | 11:03 |
| _florent_ | if using the RS232PHY, disabling the dynamic baudrate could help: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L136 | 11:03 |
| _florent_ | acathla: we you are out it RAM, RAM is implemented in Luts, which can cause this behavior | 11:04 |
| _florent_ | we/when | 11:05 |
| acathla | I tried that and it seems to help. I tried to understand https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L126-L129 a long time ago and forgot to take notes... | 11:05 |
| acathla | _florent_, even when not out of RAM at all sometime it seems it prefers to use LC. | 11:06 |
| acathla | Calculations are for a real RS232 UART | 11:06 |
| _florent_ | acathla: could you eventually do a test? | 11:07 |
| _florent_ | here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L136-L138 | 11:07 |
| _florent_ | comment: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L136 | 11:07 |
| acathla | I was using UART class with a custom PHY, now I exploded parts of the code to separate RX and TX | 11:07 |
| _florent_ | and use a static tuning_word value here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L137-L138 | 11:08 |
| _florent_ | this should reduce resource usage, is significant we could add a parameter to disable dynamic baudrate | 11:09 |
| acathla | I'll re-do that and measure | 11:10 |
| _florent_ | ok thanks | 11:10 |
| acathla | _florent_, 114 LC ! For only one UART | 11:15 |
| _florent_ | acathla: instead of 317? | 11:16 |
| acathla | 114 LC less without the register than with it | 11:16 |
| acathla | 203 instead of 317 if you prefere | 11:17 |
| _florent_ | ah ok, so that could be worth adding a parameter! (and even disable dynamic baudrate by default since I'm not sure anyone use it) | 11:17 |
| acathla | That's a good idea. I'm not using USB anymore so I can now fit icache + 1cycle mult + 1cycle shift and the rest of my design (4 Infrared transceivers) | 11:40 |
| acathla | 1 cycle shift takes 126 LC | 11:41 |
| acathla | Hum, that's not linear... | 11:43 |
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| nickoe | _florent_: What does that "BIST" stuff mean or refer to? I mean I see it mentione in the files, but I don't really understand what it is about. | 12:28 |
| nickoe | Ahh, I see """Built In Self Test (BIST) modules for testing LiteDRAM functionality.""" | 12:33 |
| nickoe | Is that what is used to do the memtests? | 12:33 |
| nickoe | in the bios? | 12:33 |
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| _florent_ | nickoe: the memtest from the CPU is a good diagnostic but not stressing that much the memory. The BIST is using hardware generator/checker to write/read at the maximum speed and with optional random data/addressing. | 14:07 |
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| nickoe | _florent_: Is there an example on how to use that to verify ddr ram settings for the platform comoletely? | 14:27 |
| tmbinc | _florent_: Makes sense. I'll put that under 360nosc0pe repo and make sure I'll rebase on top of yours. Is there a similar setup for other boards/ | 14:29 |
| tmbinc | Would be great if thereÃ's a standard way to handle this | 14:29 |
| _florent_ | nickoe: you can just set with_bist to True in add_sdram: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1187 | 14:32 |
| _florent_ | nickoe: you'll then have a sdram_bist command available in the BIOS | 14:32 |
| _florent_ | tmbinc: I'm doing this in some benches for the cores, 2s that I find an example | 14:34 |
| _florent_ | tmbinc: here for example: https://github.com/enjoy-digital/litesdcard/blob/master/bench/arty.py | 14:35 |
| _florent_ | It's a specialized bench for LiteSDCard based on the Arty platform/target from LiteX-Boards | 14:35 |
| _florent_ | so you reuse all from BaseSoC in LiteX-Boards and then add your own peripherals | 14:36 |
| _florent_ | but will depends from cases, sometimes it's also more convenient to only use the platform from LiteX-Boards and duplicate part of the target in the project | 14:37 |
| _florent_ | I'm using this second method in the LiteDRAM bench for example: https://github.com/enjoy-digital/litedram/blob/master/bench/arty.py | 14:38 |
| _florent_ | since need specific clocking/peripherals | 14:38 |
| _florent_ | maybe in 360nosc0pe you can have a copy of the platform/target from LiteX-Boards that we will customize and as progress are made we could integrate changes in LiteX-Boards if this is useful | 14:40 |
| tmbinc | ok that sounds reasonable. Let me continue in 360nosc0pe then (and we can still figure out the details later). | 14:40 |
| tmbinc | What about the memory IOSTANDARD? the chips (K4B2G1646FBYMA) seem to be DDR3 not DDR3L so they should use SSTL_1.5 not 1.35 | 14:42 |
| tmbinc | which matches the LVCMOS15 VCCQ that is used for the other ios | 14:43 |
| tmbinc | (which are on the same bank as some of the DDR IOs) | 14:44 |
| _florent_ | tmbinc: indeed, that's probably a copy/paste error on my side while copying ddram pins definition from another platform, I can do the changes, test and update LiteX-Boards | 14:48 |
| tmbinc | _florent_: Ok. Shoudl we still add the SPI bus and pin definitions for the other peripherals (even if there's no user then) to regular litex-boards? | 14:50 |
| _florent_ | that's what we are trying to do generally yes, but for test it's also possible to include this in a target file: https://github.com/enjoy-digital/litesdcard/blob/master/bench/arty.py#L55-L62 | 14:52 |
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| _florent_ | tmbinc: https://github.com/litex-hub/litex-boards/commit/975150ca6870375f56001f32f881154ae1514084 | 16:34 |
| _florent_ | I also just tested it on hardware | 16:34 |
| _florent_ | ah sorry, just saw this was already fixed in your branch... | 16:36 |
| acathla | Ok, I need help : VexRiscV without icache : 4336 LC, VexRiscV with iCacheSize 1024 : 4243 LC. How is it possible to have a negative cost to add a nice feature? | 16:46 |
| tmbinc | _florent_: thanks! (I'm sorry - I should have split my up the PR) | 17:08 |
| mithro | _florent_: Does the pythondata-misc-opentitan repository look okay? | 17:15 |
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| _florent_ | mithro: yes thanks, thanks for noticing that ibex was already in opentitan repo | 17:34 |
| mithro | We could make the pythondata-cpu-ibex just be a dummy package which depends on pythondata-misc-opentitan ? | 17:36 |
| _florent_ | mithro: yes, don't know pythondata-cpu-ibex is worth now that we know it's already in opentitan? | 17:38 |
| mithro | It's not like we have to "do" anything to maintain it however... | 17:38 |
| _florent_ | but it's still one package that has for now no utility if we use the code from opentitan :) | 17:40 |
| _florent_ | but if we can have a package called pythondata-cpu-ibex that has both ibex and the fex opentitan prim libs that are used, I can use just this one | 17:42 |
| mithro | _florent_: The less we do changes / modify the upstream repository the less likely it will break in the future | 17:43 |
| _florent_ | I meant: if pythondata-cpu-ibex is just a copy of pythondata-misc-opentitan, that also fine for me | 17:44 |
| nickoe | _florent_: What optoins should I use for sdram_bist? sdram_bist <burst_length> <random> | 17:49 |
| _florent_ | you can try sdram_bist 128 0 (no random) and sdram_bist 128 1 | 17:50 |
| nickoe | it looks like this for example, https://dpaste.com/34LQR32PX.txt | 17:50 |
| nickoe | oh, that looks different, https://dpaste.com/H3XNGP8MG.txt | 17:50 |
| nickoe | when does it stop? | 17:51 |
| _florent_ | when you press a key :) | 17:51 |
| _florent_ | do you have errors with sdram_bist 128 1? | 17:52 |
| _florent_ | the max burst length supported is 256 IIRC | 17:52 |
| nickoe | after a while, https://dpaste.com/GJETP4LZF | 17:53 |
| tpb | Title: dpaste: GJETP4LZF (at dpaste.com) | 17:53 |
| nickoe | I am not sure what to make of that.. | 17:54 |
| _florent_ | you were saying previously that you had occasional memtest failures? | 17:55 |
| nickoe | yes | 17:55 |
| nickoe | Like, after flashing | 17:56 |
| nickoe | https://github.com/nickoe/litedram/commit/1f70587e4cdfa6639174d0451efed2826b8e6aae | 17:56 |
| _florent_ | can you share the calibration log? | 17:56 |
| _florent_ | you could try to use https://github.com/enjoy-digital/litedram/blob/master/bench/ddr3_mr_gen.py to change the electrical settings directly from the BIOS | 17:57 |
| nickoe | this thing? https://dpaste.com/CD2M5NE55 | 17:57 |
| tpb | Title: dpaste: CD2M5NE55 (at dpaste.com) | 17:57 |
| _florent_ | yes | 17:58 |
| _florent_ | this looks fine | 17:58 |
| _florent_ | for ddr3_mr_gen, you can get cl/cwl from the BIOS log | 17:58 |
| _florent_ | then you can try to play with --rtt-nom --rtt-wr --rtt --ron | 17:59 |
| _florent_ | ex: ./ddr3_mr_gen.py --cl=5 --cwl=5 --rtt-nom=60ohm | 18:00 |
| _florent_ | this will generate commands that you can copy-paste to the BIOS | 18:00 |
| _florent_ | you can then to sdram_cal | 18:01 |
| _florent_ | sdram_test | 18:01 |
| _florent_ | and sdram_bist 128 1 | 18:01 |
| _florent_ | and see if it improves things | 18:01 |
| nickoe | mmm https://dpaste.com/E52ZNNU5Z | 18:01 |
| tpb | Title: dpaste: E52ZNNU5Z (at dpaste.com) | 18:01 |
| _florent_ | ok sorry, that's --rtt_nomù | 18:02 |
| _florent_ | --rtt_nom | 18:02 |
| _florent_ | but don't use cl=5 / cwl=5, you should use the ones you have in the BIOS log | 18:03 |
| nickoe | ugh, lots of errors, https://dpaste.com/AAE37GJK6 | 18:04 |
| tpb | Title: dpaste: AAE37GJK6 (at dpaste.com) | 18:04 |
| nickoe | mmm | 18:04 |
| nickoe | I am not sure what number I should look for. | 18:04 |
| nickoe | I mean there is no cl or cwl in the bios log. | 18:08 |
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| _florent_ | before the initialization, you should have SDRAM: .... (CL-X CWL-Y) | 18:10 |
| nickoe | SDRAM:262144KiB 16-bit @ 800MT/s (CL-6 CWL-5) ? | 18:11 |
| _florent_ | yes | 18:11 |
| nickoe | it seems to be the same | 18:13 |
| _florent_ | so you can try: ./ddr3_mr_gen.py --cl=6 --cwl=5 --rtt_nom=60ohm --rtt_wr=60ohm --ron=34ohm | 18:13 |
| nickoe | https://dpaste.com/3L95KXRHS | 18:13 |
| tpb | Title: dpaste: 3L95KXRHS (at dpaste.com) | 18:13 |
| _florent_ | are you doing sdram_cal after the copy/paste? | 18:13 |
| nickoe | yes | 18:15 |
| nickoe | it should be visible in the log, https://dpaste.com/2V9JPY4W5 | 18:15 |
| tpb | Title: dpaste: 2V9JPY4W5 (at dpaste.com) | 18:15 |
| nickoe | do I need to reflash or reboot? | 18:15 |
| _florent_ | ok, so with this you are using the default values (that are also the default values of the BIOS) and you can now change --rtt_nom --rtt_wr --ron and see if it improves things or not. If not, this could be a timing an issue in the DDR3 module definition | 18:15 |
| nickoe | you mean this? https://github.com/nickoe/litedram/commit/1f70587e4cdfa6639174d0451efed2826b8e6aae | 18:16 |
| _florent_ | yes | 18:17 |
| _florent_ | eventually, you can also do a test with --cl=7 | 18:17 |
| nickoe | cl=7 also errors, but slightly slower -- maybe, https://dpaste.com/BPZMTMH7C | 18:19 |
| tpb | Title: dpaste: BPZMTMH7C (at dpaste.com) | 18:19 |
| nickoe | This should be the datasheet for the ram https://www.nanya.com/Files/696?Filename=2Gb_DDR3_I_Die_component_Datasheet.pdf&ProductId=3,771 | 18:19 |
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| nickoe | I tried to adjust them a bit, maybe ti will work better onw. | 18:27 |
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| nickoe | mm, about the same. | 18:31 |
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| _florent_ | it seems you are using SSTL135 while it should be SSTL15: https://ohwr.org/project/fmc-mtlu-gw/commit/3ac8a4735350beb7c8220690dfabbde96fc0f69b?expanded=1 | 18:40 |
| tpb | Title: Adding Vivado constraints file for Enclustra AX3/PM3 with fmcTLU-c attached (3ac8a473) · Commits · Projects / AIDA-2020 TLU - Gateware · Open Hardware Repository (at ohwr.org) | 18:40 |
| _florent_ | can you change it? | 18:40 |
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| _florent_ | also be sure to change INTERNAL_VREF to 0.750: https://github.com/nickoe/litex-boards/blob/mars_ax3/litex_boards/platforms/mars_ax3.py#L140 | 18:41 |
| nickoe | mm, they listed something in https://github.com/enclustra/Mars_AX3_PM3_Reference_Design/blob/cc73a6d4db420303faa1497ef57131e6c4bd3afe/src/mig.prj#L102 | 18:41 |
| nickoe | hmm, yeah, maybe I reverted that change at some point, I am certainly not using that now | 18:42 |
| _florent_ | you are already using SSTL15? | 18:43 |
| nickoe | mm, io standard? | 18:44 |
| nickoe | it lists SSTL135 in the platform | 18:45 |
| _florent_ | yes but it's SSTL15 in the mig.prj: https://github.com/enclustra/Mars_AX3_PM3_Reference_Design/blob/cc73a6d4db420303faa1497ef57131e6c4bd3afe/src/mig.prj#L45 | 18:46 |
| nickoe | SoI specifically try to enable the low voltage mode, https://github.com/nickoe/litex-boards/blob/mars_ax3/litex_boards/platforms/mars_ax3.py#L76-L83 | 18:46 |
| nickoe | maybe I should try that instead? | 18:47 |
| _florent_ | I would first try to get it working with the MIG's settings at 1.5V | 18:48 |
| nickoe | mmm, something is not good.. ohh, yeah, forgot the voltage reference pin https://dpaste.com/4J9XTQGPM | 18:57 |
| tpb | Title: dpaste: 4J9XTQGPM (at dpaste.com) | 18:57 |
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| _florent_ | acathla: https://github.com/enjoy-digital/litex/commit/285bb96278a5e7d0682c41d0658548958f516857 | 19:02 |
| nickoe | mm, still no good after that. | 19:02 |
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| acathla | _florent_, cool, thanks | 19:07 |
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| nickoe | _florent_: The settings that they use in the mig project, are thsye for 800 timings? It appears so for me. Anyway, with 1.5V AND 800 timings from my current litedram timings config, it seems to work STABLE! :D | 19:45 |
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| shorne_ | somlo: I think I reproduced the timeout issue setting max_blk_count to the default of 8 I got a kernel lockup in sdcard_wait_done() in send_cmd | 21:34 |
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| somlo | shorne_: thanks for confirming! I'm staring at the FSMs in LiteSDCard -- I could have really used the whiteboard I have at the office :) | 21:45 |
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