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| tester | Hi all | 11:29 |
|---|---|---|
| tester | i Have guestion about generation hardware board files | 11:29 |
| tester | How can i generate HW project base on this files : | 11:30 |
| tester | https://github.com/enjoy-digital/litex/tree/master/litex/build/microsemi/*.py | 11:30 |
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| tester | Do you have any direction for me ? | 11:31 |
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| tester | Any people use HW board , and know how can i generate it ? | 11:38 |
| tester | Please | 11:38 |
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| nickoe | tester: I don't think those are generated, but written. | 17:35 |
| _florent_ | Hi tester, the files in build are used to generate the project files from the LiteX platform/target. You are not going to call them directly, you need to execute your target file. | 18:01 |
| nickoe | _florent_: If it takes a long time to erase the flash chip, and it never seem to complete, but I am using a pin definition that worked on the older litex from litex-buildenv, what could be the issue? | 18:09 |
| nickoe | https://github.com/nickoe/litex-boards/blob/mars_ax3/litex_boards/targets/mars_ax3.py#L104-L132 | 18:13 |
| nickoe | Hmm, I have this module I am making. I am trying to connect a register to some pins/pads. https://dpaste.com/9FG93ZAJN But it does not seem like anything gets out on the pins | 18:51 |
| tpb | Title: dpaste: 9FG93ZAJN (at dpaste.com) | 18:51 |
| nickoe | is there something syntactically I am doing wrong? | 18:51 |
| nickoe | the platform definition looks like this, https://dpaste.com/7XU824DXP | 18:53 |
| tpb | Title: dpaste: 7XU824DXP (at dpaste.com) | 18:53 |
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| nickoe | ahh, I forgot to add the eq things to the comb list! | 19:13 |
| nickoe | the signal leves does not look that strong though | 19:18 |
| nickoe | mm, well, it do work on some pins.. mmm | 19:39 |
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| nickoe | Not really sure why it appears that only one of the bus outputs work.. https://i.snipboard.io/xRtzPy.jpg | 20:43 |
| nickoe | oh, found it | 20:49 |
| nickoe | I did insert the "a" storage to the comb twice instead of both a and b | 20:50 |
| nickoe | uhg, but now memory init fails completely | 20:55 |
| nickoe | yay https://i.snipboard.io/ugHrjK.jpg | 21:02 |
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| nickoe | _florent_: I have these RAM parameters, https://github.com/enjoy-digital/litedram/compare/master...nickoe:mars_ax3 | 21:30 |
| nickoe | _florent_: If I want those merged, can we do that without submitting the board? Then I won't have as many forked dependencies in my project. .... but what I really ask, is there a proper way to testif those parameters work properly? | 21:31 |
| nickoe | I am using them now, often when I boot I get a couple of errors in memcheck but a subsequent sdram_initor sdram_test passes OK. I wonder if that is just the PLL that is not ready yeat? Or maybe some timing constraits that are not fully matched in the vivado syth. | 21:32 |
| nickoe | Mm, I guess I could just put that in my platform file as well, to keep it together for now. | 21:35 |
| nickoe | ? | 21:35 |
| nickoe | _florent_: I wonder if this could be the issue for the flash not behaving? | 22:17 |
| nickoe | WARNING: [Synth 8-7023] instance 'STARTUPE2' of module 'STARTUPE2' has 13 connections declared, but only 9 given [/home/nickoe/litex_test/dangerous_litex/litex-boards/litex_boards/targets/build/mars_ax3/gateware/mars_ax3.v:12923] | 22:17 |
| nickoe | The code where I copied the flash stuff from uses that STARTUPE2 | 22:17 |
| nickoe | not hat I completely understand what it does | 22:17 |
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