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geertu | Anyone else getting this? | 15:23 |
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geertu | Can't open input file `litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ood_Wm.v' for reading: No such file or directory | 15:23 |
geertu | I do have the updated litex_setup.py that does the submodule update | 15:24 |
geertu | Doing a manual submodule update doesn't make a difference | 15:24 |
geertu | _florent_: Building now after reverting dee4331dc39124bc ("make/soc_linux: use Wishbone memory accesses/L2 cache on boards not supporting direct LiteDRAM interface (no DM supoport).") | 15:34 |
geertu | The result hangs after Liftoff!, though :-( | 15:53 |
geertu | Not easy to bisect, due to interdependencies among linux-on-litex-vexriscv, litex, litex-boards, ... | 16:15 |
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_florent_ | geertu: have you try doing a git submodule update --init --recursive in pythondata-cpu-vexriscv-smp? | 16:58 |
_florent_ | try/tried | 16:58 |
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geertu | _florent_: I hadn't tried the --recursive. Just did, and no difference | 18:48 |
geertu | litex_setup.py had have done the --recursive before anyway | 18:52 |
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