Friday, 2021-01-29

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geertuAnyone else getting this?15:23
geertuCan't open input file `litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ood_Wm.v' for reading: No such file or directory15:23
geertuI do have the updated litex_setup.py that does the submodule update15:24
geertuDoing a manual submodule update doesn't make a difference15:24
geertu_florent_: Building now after reverting dee4331dc39124bc ("make/soc_linux: use Wishbone memory accesses/L2 cache on boards not supporting direct LiteDRAM interface (no DM supoport).")15:34
geertuThe result hangs after Liftoff!, though :-(15:53
geertuNot easy to bisect, due to interdependencies among linux-on-litex-vexriscv, litex, litex-boards, ...16:15
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_florent_geertu: have you try doing a git submodule update --init --recursive in pythondata-cpu-vexriscv-smp?16:58
_florent_try/tried16:58
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geertu_florent_: I hadn't tried the --recursive. Just did, and no difference18:48
geertulitex_setup.py had have done the --recursive before anyway18:52
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