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| somlo | shorne: got a notification from the kernel test robot (with you in the cc) re. the "move generic accessors to litex.h" -- any idea, is that a real problem or a glitch in the testing infrastructure ? :) | 14:59 |
|---|---|---|
| geertu | somlo: Is it bad? Was it CCed to a public list? | 15:13 |
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| somlo | geertu: forwarded it to you (yes mailing list in the cc, but I'd have to do "research" to find a public link :) | 16:43 |
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| geertu | somlo: thx | 16:45 |
| geertu | Looks fishy | 16:45 |
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| geertu | btw, http://lore.kernel.org/r/<msgid> | 16:46 |
| somlo | yeah, can't see how it's related to the patch it's actually complaining about :) | 16:46 |
| somlo | geertu: thanks for the msgid link-fu, I'll have to remember that! :) | 16:49 |
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| geertu | somlo: That .config seems to be completely broken. I get lots of | 16:50 |
| geertu | sh4-linux-gnu-objcopy: Unable to change endianness of input file(s) | 16:50 |
| geertu | sh4-linux-gnu-ld: cannot find certs/.tmp_gl_system_keyring.o: No such file or directory | 16:50 |
| geertu | => ignore | 16:51 |
| somlo | yeah, tried to reproduce it yesterday, got a total incomprehensible mess, which leads me to suspect the kernel test robot is having a "moment" :) | 16:51 |
| somlo | but needed a sanity check to be sure... | 16:51 |
| somlo | thanks! | 16:51 |
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| geertu | somlo: The robot is right in that drivers/soc/litex/litex_soc_ctrl.o regressed due to your commit. But since everything else is broken, too, that doesn't matter. | 16:54 |
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| somlo | geertu: ok, for now I'll go with "return -EWORKSFORME", and assume that either nothing is wrong, or someone will send a bug report that at least one of us can comprehend :) | 16:57 |
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| acathla | I made a capture with LiteScope on a versa-ecp5 : http://acathla.tk/LiteX/Capture%20d%E2%80%99%C3%A9cran_2021-01-27_18-25-12.png | 17:28 |
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| acathla | I don't what's the CPU is doing between two writes to an UART (CSR). It takes 42 cycles here, 156 on a Fomu | 17:30 |
| acathla | _florent_, I made a capture with litescope : http://acathla.tk/LiteX/Capture%20d%E2%80%99%C3%A9cran_2021-01-27_18-25-12.png and the VCD : http://acathla.tk/LiteX/dump_versa_writes_in_42_cycles.vcd | 17:31 |
| acathla | I don't know how to debug more, and what to do now. | 17:31 |
| mithro | _florent_: Still got some work to do to catch up with Chisel! https://usercontent.irccloud-cdn.com/file/iR1F1Mqy/image.png | 17:32 |
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| zyp | acathla, it's waiting | 17:48 |
| acathla | zyp, waiting for a signal? | 17:49 |
| zyp | acathla, dbus_cyc goes high when the cpu is trying to write, dbus_ack goes high when the write completes | 17:49 |
| zyp | looks like roughly two thirds of the time is spent just waiting for the write to go through | 17:50 |
| acathla | what could take so many cycles? | 17:50 |
| zyp | bus bridges, adapters, etc, I guess | 17:50 |
| acathla | Are there some wishbone signals I could watch? | 17:51 |
| zyp | cyc/stb on all the other wishbone segments involved | 17:54 |
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| somlo | acathla: it's not unusual for a cpu write to have to wait many (sometimes hundreds) of clock cycles for the valid/ready (or RTS/CTS) strobes to line up; I just never thought about LiteX in particular -- one would expect it's less of a problem here, since the cpu and memory clocks don | 18:36 |
| somlo | don't differ by so many orders of magnitude; but apparently it's still a thing | 18:36 |
| somlo | whether it's a real problem or just "the way things are", I am not qualified to say, but it shouldn't be super shocking, is all I'm saying :) | 18:37 |
| acathla | somlo, on a fomu/iCE40 @ 12MHz, I made some captures where it takes exactly 156 cycles between two writes | 18:38 |
| somlo | also depends on whether you're writing to a CSR, SRAM, or DRAM (the latter of which is likely involving LiteDRAM plus the actual memory, so it gets complicated) | 18:39 |
| somlo | acathla: just curious: is there a difference between a CSR (MMIO register) for a device, and SRAM (e.g. the stack used by the bios)? | 18:40 |
| acathla | somlo, I didn't check that. | 18:41 |
| acathla | I'm trying to write to a CSR UART | 18:41 |
| acathla | I'm shocked because I cannot fill a FIFO in parallel for an UART running at... roughtly 500KHz | 18:43 |
| acathla | I mean, it sends a byte every 1.8µs | 18:44 |
| acathla | Hum ,that's a measurement @20MHz, not 12, but that's almost the same | 18:45 |
| zyp | I think it's unreasonably slow FWIW | 18:46 |
| zyp | but there's obviously a reason it's that slow, so the question is what is blocking | 18:47 |
| zyp | acathla, can you try adding bus_interconnect also to the litescope capture? | 18:52 |
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| zyp | acathla, actually, looking closer at your trace, it seems to be taking 21 cycles, not 42 | 19:01 |
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| zyp | I guess the issue here is that it's using a shared interconnect which is not very efficient, so it appears there's 8 ibus fetches, each consuming two cycles, making up 16 of the cycles, and those appear to be blocking the dbus | 19:10 |
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| zyp | once the ibus runs out of things to fetch, it releases cyc, allowing the interconnect to switch to serving the dbus, letting the write go through | 19:11 |
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| zyp | I might be totally mistaken, but if this works out to 21 cycles for one iteration of a 8 instruction write loop through an inefficient interconnect, it's fairly understandable | 19:13 |
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| acathla | zyp, thank you for those explanations. How can I add bus_interconnect? | 21:55 |
| zyp | same way you added cpu and uart :) | 21:56 |
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| acathla | but interconnect is added automatically, what's it's name in python/Litex? | 21:59 |
| acathla | I found some builder_csr_interconnect in the verilog output | 22:00 |
| zyp | I think the name is bus_interconnect, but I'm not sure | 22:04 |
| acathla | zyp, I found soc.cpu because it's in the examples, but since I didn't add it manually, I don't know how to find it's name | 22:05 |
| zyp | just try soc.bus_interconnect | 22:06 |
| acathla | it does not work | 22:07 |
| acathla | but in verilog, most added things, CPU, UART, RAM are named main_something, and there is some builder_csr_interconnect_adr. | 22:09 |
| acathla | Time to sleep | 22:16 |
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