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| futarisIRCcloud | litex mentioned in Microwatt grows up at lca 2021. https://lca2021.linux.org.au/schedule/presentation/61/ | 03:32 |
|---|---|---|
| tpb | Title: linux.conf.au 2021 | Presentation: Microwatt grows up (at lca2021.linux.org.au) | 03:32 |
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| _florent_ | futarisIRCcloud: Thanks, time flies! | 10:23 |
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| cr1901_modern | _florent_: Wanna feel old? You've been running your company for as long as I've known how to use FPGAs (minus one year- I learned in early 2010) | 13:26 |
| daveshah | I started playing with FPGAs in 2015... | 13:32 |
| zyp | I started playing with FPGAs in 2007, but I never progressed much from there, so I'm still a novice :) | 13:34 |
| geertu | daveshah: You used a very impressive learning curve ;-) | 13:34 |
| cr1901_modern | daveshah: I fell out of love w/ them in 2012, but fell back "in love" with them in 2015. So that would be a 3 year gap where I didn't touch them lol | 13:35 |
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| Melkhior | Hello, I'm trying to get linux-on-rocket-litex to work on my board, but the memory fails (bus errors: 0/256 addr errors: 8192/8192 data errors: 524288/524288). A similar configuration with VexRiscV works fine. However VexRiscV is running at 100 MHz,with the memory at 800 MT/s. Rocket is running at 50 MHz with the memory at only 400 MT/s. Could | 14:51 |
| Melkhior | that be the reason ? | 14:51 |
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| Melkhior | (Artix 7, 35K, SoC barely fit but passes timing at 50 MHz, yet to try higher clock) | 14:52 |
| daveshah | Yes, there have been problems with running litedram at reduced clocks in the past | 14:53 |
| daveshah | I thought they had been fixed but evidently not. Can you see if a 50MHz VexRiscv also fails? | 14:53 |
| Melkhior | Thanks. Any way to run the memory at more than 4x the CPU clock ? | 14:54 |
| daveshah | Not sure, I don't think it would be possible without some big changes but _florent_ is the one to comment there | 14:54 |
| Melkhior | IIRC, never tried a slower VexRiscV. Will try to find the time to test that, it would help narrow the issue. | 14:55 |
| daveshah | yeah | 14:55 |
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| Melkhior | With rocket at 66 MHz (and at 75 MHz but some minor negative slack so might not be relevant) memory fails as well. | 15:49 |
| Melkhior | With VexRiscV at 66 MHz memory fails as well | 15:49 |
| Melkhior | Guess the board requires a fast controller | 15:49 |
| Melkhior | Synthesizing VR5 @ 80 MHz now ... | 15:49 |
| Melkhior | Sorry @ 75 MHz as well, PLL failed for 80 MHz | 15:50 |
| daveshah | This is really something that should be fixeable in litedram, we managed to make lower frequencies work successfully for ECP5 in the end | 15:51 |
| daveshah | unfortunately, it's also beyond my experience to suggest how to fix it... | 15:51 |
| Melkhior | VexRiscV should let me figure out what's the 'minimum' speed | 15:53 |
| Melkhior | I wanted to try Rocket but it's far from critical | 15:54 |
| Melkhior | I have a lowly Artix 7 35K -1, Rocket might work on a bigger/higher speed grade FPGA | 15:56 |
| Melkhior | With VexRiscV at 75 MHz memory fails as well, no surprise | 15:57 |
| Melkhior | Thanks for the help | 15:57 |
| felix_ | _florent_: congrats! | 15:59 |
| _florent_ | Melkhior: We are not able to do a proper write leveling on Artix7 due to the lack of ODELAYE2 (that are present on Kintex7 and Ultrascale), we are using a shifted sys4x_dqs to compensate: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/arty.py#L47, that's possible some manual adjustments will be required on it to run at a frequency lower than 75MHz on Arty | 16:03 |
| _florent_ | Melkhior: but it seems I was running the bench on Arty between a 60MHz clock and 150MHz clock, so 66 and 75 should pass: https://github.com/enjoy-digital/litedram/blob/master/bench/arty.py#L159-L160 | 16:05 |
| Melkhior | With VexRiscV at 82.67 Mhz memory works fine... | 16:06 |
| Melkhior | _florent_ Thanks.. but to be honest I don't understand what it means:-) (OLDELAYE2 is mentioned in https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf I'll have to look at that) | 16:06 |
| _florent_ | felix_: thanks | 16:06 |
| Melkhior | _florent_ Similar FPGA, different board (and memory device) https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html (version 2.13a in my case) with MT41J128M16 | 16:08 |
| tpb | Title: USB-FPGA Module 2.13: FPGA Board with Artix 7, EZ-USB FX2 and DDR3 SDRAM. (at www.ztex.de) | 16:08 |
| _florent_ | Melkhior: ah, you are not testing on Arty? | 16:08 |
| Melkhior | No, the Ztex board + my SBus carrier to supply the micro-sd card slot | 16:09 |
| Melkhior | Do you think I should upstream my platforms/targets for them ? | 16:10 |
| _florent_ | we could if it's not too specific | 16:14 |
| _florent_ | Melkhior: I just tested 75MHz on Arty, it's passing, going to test 60MHz | 16:16 |
| Melkhior | standalone ZTex is commercially available, but has no peripherals so I have the LEDs for the debug board ; my carrier is OSHW but I doubt anyone will build one :-) | 16:16 |
| Melkhior | is there some simple procedure for that test I could try? | 16:17 |
| Melkhior | need to fix bench/arty.py to create bench/ztex.py for a start I guess | 16:21 |
| _florent_ | Melkhior: yes you can do some tests, can you copy/paste these magic commands?: | 16:22 |
| _florent_ | https://www.irccloud.com/pastebin/m00G0X9C/ | 16:22 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 16:22 |
| _florent_ | in the BIOS | 16:22 |
| _florent_ | if working, I'll explain :) | 16:22 |
| andrewb1999 | _florent_: Related question, are you using the arty design that uses an S7PLL or an S7MMCM? I have been using S7PLL as symbiflow doesn't fully support MMCM yet but I have noticed less stable DRAM even with vivado. | 16:23 |
| Melkhior | ... at some specific speed or any will do ? (I have a 82.67 MHz loaded) | 16:23 |
| Melkhior | I have S7MMCM in my targets/*ztex.py, using Vivado | 16:26 |
| _florent_ | Melkhior: test it at a speed that is was not working, ex 60 or 75MHz | 16:27 |
| Melkhior | OK, will have to regenerate the bitstream to test | 16:27 |
| Melkhior | will report | 16:27 |
| Melkhior | thanks for the help ! | 16:28 |
| _florent_ | Melkhior: can you also share the results of the calibration when testing? This can be useful to understand | 16:30 |
| Melkhior | sure, will do | 16:30 |
| _florent_ | andrewb1999: I'm testing with the LiteX-Boards Arty target: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/arty.py#L42 | 16:31 |
| andrewb1999 | _florent_: Ah ok, so you are using the S7PLL version. Good to know. | 16:32 |
| _florent_ | andrewb1999: no sure I tested much with a MMCM, I know there are still things to investigate with Symbiflow: https://github.com/enjoy-digital/litex/issues/751 | 16:32 |
| _florent_ | andrewb1999: in case you have troubles with the LiteDRAM on Arty with Vivado, please fill an issue on LiteX (with the logs of the calibration), I'll have a look | 16:35 |
| andrewb1999 | _florent_: Will do that when I have a chance. | 16:37 |
| Melkhior | _florent_ With a 60 MHz VexRiscV, your magic commands make things work | 17:13 |
| Melkhior | Switching SDRAM to software control. | 17:13 |
| Melkhior | Write latency calibration: | 17:13 |
| Melkhior | m0:0 m1:0 | 17:13 |
| Melkhior | Read leveling: | 17:13 |
| Melkhior | m0, b0: |00000000000000000000000000000000| delays: - | 17:13 |
| Melkhior | m0, b1: |11111111111111111111110000000000| delays: 11+-11 | 17:13 |
| Melkhior | m0, b2: |00000000000000000000000011111111| delays: 28+-04 | 17:13 |
| Melkhior | m0, b3: |00000000000000000000000000000000| delays: - | 17:13 |
| Melkhior | m0, b4: |00000000000000000000000000000000| delays: - | 17:13 |
| Melkhior | m0, b5: |00000000000000000000000000000000| delays: - | 17:13 |
| Melkhior | m0, b6: |00000000000000000000000000000000| delays: - | 17:13 |
| Melkhior | m0, b7: |00000000000000000000000000000000| delays: - | 17:13 |
| Melkhior | best: m0, b01 delays: 11+-11 | 17:13 |
| Melkhior | m1, b0: |00000000000000000000000000000000| delays: - | 17:13 |
| Melkhior | m1, b1: |11111111111111111111111000000000| delays: 11+-11 | 17:13 |
| Melkhior | m1, b2: |00000000000000000000000111111111| delays: 28+-04 | 17:13 |
| Melkhior | m1, b3: |00000000000000000000000000000000| delays: - | 17:13 |
| somlo | Melkhior: ok, so now does that same trick work with Rocket? :) Sorry, don't have an Arty board to try for myself... | 17:21 |
| Melkhior | on it :-) | 17:21 |
| Melkhior | it works, but Rocket won't boot the VexRiscV kernel ;-) | 17:22 |
| somlo | try the boot.bin for nexys4ddr (https://github.com/litex-hub/linux-on-litex-rocket/issues/1) | 17:23 |
| somlo | it will probably hang if you don't have a sdcard or ethernet or if they're at different MMIO addresses than the hard-coded DTB in that blob | 17:24 |
| somlo | but at least the kernel should hopefully start booting, which should be good to know... | 17:24 |
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| Zguig | https://freenode.irclog.whitequark.org is down... :( | 17:28 |
| somlo | _florent_: Happy 10-year Anniversary! :) :) | 17:28 |
| _florent_ | Melkhior: ok thanks for the test. So for now you could patch https://github.com/enjoy-digital/litedram/blob/master/litedram/init.py#L119 and use cl = phy_settings.cl + 1 | 17:29 |
| _florent_ | Melkhior: I'll try to look at it soon | 17:29 |
| _florent_ | somlo: thanks! I'm feeling old with this... (even if "only" 35 :)) | 17:36 |
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| somlo | experience has taught me that 35 is *not* old ;) | 17:44 |
| Melkhior | somlo I had compiled my own boot.bin, but it doesn't work; not sure if it fails to load or fails to run: | 17:44 |
| Melkhior | litex> sdcardboot | 17:44 |
| Melkhior | Booting from SDCard in SD-Mode... | 17:44 |
| Melkhior | Booting from boot.json... | 17:44 |
| Melkhior | boot.json file not found. | 17:44 |
| Melkhior | Booting from boot.bin... | 17:44 |
| Melkhior | Copying boot.bin to 0x80000000 (15701872 bytes)... | 17:44 |
| Melkhior | [ | 17:44 |
| Melkhior | ... and then nothing. | 17:45 |
| Melkhior | will have to try with yours to compare. DTS is the same than nexys4ddr, with twice the ram and no ethernet. Not sure if I fixed that properly... | 17:46 |
| somlo | sounds like the path from sdcard -> dram (dma into rocket, and axi point-to-point to litedram back out of rocket) | 17:50 |
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| somlo | so it's probably a question of what command line you used. Also, depending on the native width of litedram on the Arty, you should pick the `linux | linuxd | linuxq` variant (64 vs. 128 vs. 256 bit native litedram width) | 17:52 |
| Melkhior | Same result with your boot.bin | 17:52 |
| _florent_ | somlo: yes it seems the DMA from LiteSDCard is not able to access the DRAM | 17:52 |
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| somlo | Melkhior: right, so it doesn't matter what's in DT or the kernel, this is a bios level problem | 17:53 |
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| somlo | Melkhior: by "command line" earlier I meant the command to build your (rocket) bitstream for the Arty | 17:53 |
| Melkhior | It's still not an arty:-) I used this: | 17:54 |
| Melkhior | litex-boards/litex_boards/targets/sbustoztex.py --build --cpu-type rocket --cpu-variant linuxd --sys-clk-freq 60e6 --with-sdcard --integrated-rom-size 0x10000 | 17:54 |
| somlo | _florent_: do you happen to remember off the top of your head what the native litedram width is on the Arty ? | 17:54 |
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| Melkhior | I'm not sure I have 128 bits, I should try linux as well | 17:54 |
| somlo | oh, ok, not an arty board, I somehow assumed that from the context, might have misread it | 17:55 |
| _florent_ | somlo: that's 128-bit on Arty yes | 17:55 |
| somlo | and yeah, 128bit is linuxd | 17:55 |
| Melkhior | I can try 'linux' as well just in case, I'm pretty sure it's not linuxq | 17:56 |
| Melkhior | mmmm, the board has just the one chip, shouldn't that be 64 bits ? | 17:56 |
| Melkhior | _florent_ the +1 solves the problem for me, now w/ Rocket it passes memtest and then goes straight to the boot failure, no need for the magic commands, thanks | 17:57 |
| _florent_ | Melkhior: ok good, I'll adjust this | 17:58 |
| Melkhior | synthesizing with "linux" instead of "linuxd" to see if I'm 64 and not 128 bits on that board | 17:58 |
| Melkhior | ... how is that set up for VexRiscV ? I don't remember telling it either of those ... | 17:59 |
| _florent_ | Melkhior: if your board has a 16-bit DDR3, the native width of the controller will be128-bit | 17:59 |
| Melkhior | so it's 128-bit I think, as the documentation says to use 16-bit in Xilinx MIG | 17:59 |
| _florent_ | Melkhior: for VexRiscv we are generating the VexRiscv cluster automatically from the dram width | 18:00 |
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| Melkhior | oh that's right, now I remember: the width even appear in the Verilog filename when using SMP in my setup, it was 128 (Ldw128) | 18:02 |
| Melkhior | so definitely linuxd | 18:02 |
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| Melkhior | so the failure is elsewhere... | 18:04 |
| somlo | ok, so with Rocket there's a special DMA bus, on which the sdcard gateware has master mode, and the Rocket has a slave port | 18:04 |
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| somlo | Rocket will then route those requests through its own internal "backplane" and out over the mem_axi port that's hooked point-to-point to LiteDRAM | 18:04 |
| somlo | that path is broken somehow for you | 18:05 |
| Melkhior | OK, thanks for the explanations (and the help!) | 18:05 |
| Melkhior | Could I have broken that from a wrong DTS ? That's the only part that is really new (the board platform/targets are identical with VexRiscV, the whole SoC is straight from GitHub) | 18:06 |
| somlo | Melkhior: nope, the DTS comes into play only once boot.bin has been transfered into RAM, and execution transferred to it | 18:07 |
| Melkhior | (I'm guessing no as you seemed to think the nexys4ddr boot.bin should load...) | 18:07 |
| Melkhior | OK | 18:07 |
| Zguig9 | Hi guys, I have a few questions again. I'm working on flashspi and board ECPIX5. I had first an issue with specific clock pin as described here: https://github.com/YosysHQ/prjtrellis/issues/158 | 18:07 |
| Zguig9 | I finished by just removing the associated core clk pinout and have this finally: | 18:07 |
| Melkhior | Then I don't know what I broke :-/ | 18:07 |
| Zguig9 | # SPIFlash | 18:07 |
| Zguig9 | ("spiflash", 0, | 18:07 |
| Zguig9 | Subsignal("cs_n", Pins("AA2")), | 18:08 |
| Zguig9 | Subsignal("mosi", Pins("AE2")), | 18:08 |
| Zguig9 | Subsignal("miso", Pins("AD2")), | 18:08 |
| Zguig9 | Subsignal("wp", Pins("AF2")), | 18:08 |
| Zguig9 | Subsignal("hold", Pins("AE1")), | 18:08 |
| Zguig9 | IOStandard("LVCMOS33") | 18:08 |
| Zguig9 | ), | 18:08 |
| Zguig9 | ("spiflash4x", 0, | 18:08 |
| Zguig9 | Subsignal("cs_n", Pins("AA2")), | 18:08 |
| Zguig9 | Subsignal("dq", Pins("AE2", "AD2", "AF2", "AE1")), | 18:08 |
| Zguig9 | IOStandard("LVCMOS33") | 18:08 |
| somlo | you're firmly stuck somewhere in the LiteX bios (litex/soc/software/liblitesdcard/litesdcard.c) | 18:08 |
| somlo | Melkhior: not clear it was *you* who broke anything, it's just that nobody has ever tried Rocket+Litex on your board, and there's "unknown unknowns" to deal with whenever something like that happens :) | 18:09 |
| Melkhior | I could have a very marginal microsd-card; I designed the carrier board with the microsd-card slot - and whike it works fine with Litex/VexRiscV in SD-mode, it mostly fails in SPI mode. And I've yet to succeed to use the microsd-card in my own design for the board's "primary" purpose in my SPARCstation. | 18:12 |
| Melkhior | Rocket is in SD-mode so is in a configuration that can work hardware-wise, but there might still be issue if litesdcard is used a bit differently in Litex/Rocket vs LItex/VExRiscV ... | 18:13 |
| Melkhior | as you said - 'there's "unknown unknowns" to deal with' :-) | 18:13 |
| Melkhior | anyway thanks everyone for the help :-) | 18:14 |
| Melkhior | last question - does the Rocket BIOS support serialboot ? | 18:14 |
| Melkhior | with lxterm | 18:14 |
| Melkhior | that would bypass the problem | 18:14 |
| somlo | Maybe spi-mode sdcard will work with Rocket ? Just throwing things at the wall at this point, but I got nothing else :) | 18:14 |
| _florent_ | Melkhior: maybe you could do more testing with the sdcard_xy commands of the BIOS first | 18:15 |
| _florent_ | try to init/read/write a data block | 18:15 |
| somlo | (I got both spi- and native litesdcard going on the nexys4ddr, so "theoretically" they both should work) | 18:15 |
| somlo | and yeah, what _florent_ said | 18:15 |
| Melkhior | _florent_ for some reason I can't interrupt the boot process; the BIOS initialize the memory then goes straight to load boot.bin, can't stop it (I could re-break the memory controller that stops it ;-) ) | 18:17 |
| Melkhior | I'll rename the boot.bin | 18:18 |
| _florent_ | also, it seems the BIOS is able to copy SDCard blocks from the SDCard to the SRAM (since able to find boot.bin and the size), but not to DRAM | 18:18 |
| _florent_ | Melkhior: pressing EST or Q during during the boot should interrupt it | 18:19 |
| _florent_ | ESC | 18:19 |
| Melkhior | didn't manage to interupt even with q, but then I've a weird setup (I'm using a beaglebone white and some jumper cables as a serial console... ) | 18:20 |
| Melkhior | anyway - I can read block all right, and the first is OK (i've seen it so many times trying to fix my design I know exactly what bytes are non-zero by now... sigh ... ) | 18:21 |
| somlo | _florent_: if copying sdcard -> SRAM works on *Rocket*, then DMA routing through Rocket's backplane is OK, and we're talking the ability to send bits to LiteDRAM over the AXI dedicated link that's the problem | 18:22 |
| Melkhior | seems serialboot would work, but at 115200 sending 15+ MiB is going to be long... | 18:26 |
| Melkhior | Can I just pass '--uart-baudrate 1000000' to match LInux/VexRiscV default of a 1MBit/s serial port ? | 18:27 |
| Melkhior | Let's try and see :-) | 18:27 |
| Melkhior | anyway getting late thanks a lot for all the help :-) | 18:29 |
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| Melkhior | To finish - my boot.bin did load through serialboot, I get 'liftoff', the kernel starts and eventually stops after: | 18:48 |
| Melkhior | ... | 18:48 |
| Melkhior | [ 1.131849] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254) | 18:48 |
| Melkhior | [ 2.025180] loop: module loaded | 18:48 |
| Melkhior | [ 2.200884] libphy: Fixed MDIO Bus: probed | 18:48 |
| Melkhior | [ 2.226014] litex-mmc 12005800.mmc: Requested clk_freq=12500000: set to 12500000 via div=4 | 18:48 |
| Melkhior | [ 2.265655] NET: Registered protocol family 10 | 18:48 |
| Melkhior | [ 2.280328] Segment Routing with IPv6 | 18:48 |
| Melkhior | [ 2.281909] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver | 18:48 |
| Melkhior | [ 2.293616] NET: Registered protocol family 17 | 18:48 |
| Melkhior | I don't have Ethernet on that board (commented out in the DTS), could be that or could be the sdcard again | 18:49 |
| Melkhior | to be continued :-) | 18:49 |
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| geertu | Oops, Melkhior is gone | 19:12 |
| geertu | But a hang there may be due to the wrong L1_CACHE_SHIFT | 19:13 |
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| Melkhior | geertu Thanks for the tip, I'll have to investigate that | 20:08 |
| Melkhior | good night, depending on the timezone :-) | 20:09 |
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| acathla | How can I connect a litex_server to a litex_sim ? Through ethernet only? I added --with-analyzer to use litescope_cli. | 20:19 |
| _florent_ | acathla: yes litex_sim --with-etherbone --with-analyzer | 20:48 |
| _florent_ | litex_server --udp --udp-ip=192.168.1.51 | 20:48 |
| acathla | no uart simulation usable? | 20:48 |
| acathla | ok | 20:48 |
| _florent_ | litescope_cll | 20:48 |
| _florent_ | not yet in simulation (except the console) | 20:49 |
| acathla | hum, should it answer to ping? | 20:52 |
| acathla | _florent_, I've got a tieout | 20:52 |
| acathla | timeout | 20:52 |
| acathla | of, my mistake | 20:53 |
| acathla | answer to me: yes it answers to ping, and to litex_server if you wait a few seconds | 20:55 |
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