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| joseng | _florent_ Tested now with l2_size=0, that also disables the reversing of the data order (and the flag "l2_reverse" which is by default True does not do anything with cache size 0) | 10:54 |
|---|---|---|
| joseng | Is it recommended to have no l2 cache at all? Or can the cache somehow be disabled for the DMA readers and writers? | 10:55 |
| _florent_ | joseng: the LiteDRAMDMAReader/Writer are directly connected to the DRAM controller, so there is no caching. But if for your test you are writing/checking data from the CPU, you'll have to be sure the L2 cache is flushed before doings reads from the CPU, or disable the L2 cache as you just did. | 11:20 |
| _florent_ | The L2 cache improve performance and allow more efficient accesses to the DRAM, but you should indeed probably disable it for now (but with a potential reversing of the data as you seen, that we could try to avoid). | 11:24 |
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| somlo | _florent_: got litescope working with the actual fpga board \o/ | 12:59 |
| somlo | thanks again for the handholding! :) | 12:59 |
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| Melkhior | Hello, | 13:38 |
| Melkhior | I'm trying to get the sdcard work in SPI mode in the LiteX BIOS on my HW, and so far no luck. | 13:38 |
| Melkhior | The 'native' mode works beautifully - LiteX loads the kernel and root filesystem very fast, and everything is fine. | 13:38 |
| Melkhior | However if I use SPI mode instead, the BIOS hangs on 'Booting from boot.json...', though sometimes after some minutes I get "Booting from boot.bin..." (and occasionally after that "SDCard boot failed./No boot medium found"). | 13:38 |
| Melkhior | Any suggestion what could cause the SPI mode to fail? Or how I could try to figure out the problem? | 13:38 |
| Melkhior | Thanks in advance! | 13:38 |
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| _florent_ | Melkhior: getting SPI mode working should be easier than native mode. I would recommend checking your pins definition. | 16:08 |
| _florent_ | for reference, you can look at: | 16:08 |
| _florent_ | https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/arty.py#L285-L307 | 16:08 |
| _florent_ | https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/orangecrab.py#L161-L176 | 16:09 |
| _florent_ | you can also try lowering the clock: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/liblitesdcard/spisdcard.c#L28 | 16:10 |
| _florent_ | palmer: it's possible to run our setup in simulation (with Verilator): https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/sim.py | 16:27 |
| _florent_ | it's not very fast (5 to 10min to boot linux), but if this is useful for you, happy to help you setting this up | 16:28 |
| Melkhior | _florent_ Thanks for the advice. I triple-checked the signals (all 4 of them :-) ) that I based on the arty design. I guess they're OK as it seems the "init" part is always successful, at least that the impression I got from tracking the state of the FSM in the SPI-based controllers I've tried with my design (and with one btistream - that I can't | 17:29 |
| Melkhior | regenerate for unknown reasons - I was able to read blocks from the card... early in the process so I didn't think of saving it!). | 17:29 |
| Melkhior | I also tried lowering/raising the frequency (thanks for confirming I had the right file, it felt strange to change C code rather than HDL) - 25 MHz, 20MHz, 5MHz, 400KHz, all hangs the same way. Meanwhile, 'native' mode always just works! | 17:29 |
| Melkhior | I wish I could just use litesdcard in my design, I've managed to generate some verilog, but the interface is too complicated for my limited HW skills at this stage. I can't figure out to _not_ have a local ClockDomain & PLLs (so I can use my own 48, 50 or 100 MHz clock directly), how to expose the CSR (can I just do | 17:29 |
| Melkhior | "bus_pads.cmd_arg.eq(self.sdcore.cmd_argument.storage)" and expose them to the outside world ?), or how to talk to the source/sink... | 17:29 |
| Melkhior | The only difference between 'working' and 'non-working' is using "sdcard" or "spisdcard" in "make.py", which the board defines like this: | 17:33 |
| Melkhior | ("spisdcard", 0, | 17:33 |
| Melkhior | Subsignal("clk", Pins("R8"), Misc("PULLUP")), | 17:33 |
| Melkhior | Subsignal("mosi", Pins("T5"), Misc("PULLUP")), | 17:33 |
| Melkhior | Subsignal("cs_n", Pins("V6"), Misc("PULLUP")), | 17:33 |
| Melkhior | Subsignal("miso", Pins("V5"), Misc("PULLUP")), | 17:33 |
| Melkhior | Misc("SLEW=FAST"), | 17:33 |
| Melkhior | IOStandard("LVCMOS33"), | 17:33 |
| Melkhior | ), | 17:33 |
| Melkhior | ("sdcard", 0, | 17:33 |
| Melkhior | Subsignal("data", Pins("V5 V4 V7 V6"), Misc("PULLUP")), | 17:33 |
| Melkhior | Subsignal("cmd", Pins("T5"), Misc("PULLUP")), | 17:33 |
| Melkhior | Subsignal("clk", Pins("R8")), | 17:33 |
| Melkhior | #Subsignal("cd", Pins("V6")), | 17:33 |
| Melkhior | Misc("SLEW=FAST"), | 17:33 |
| Melkhior | IOStandard("LVCMOS33"), | 17:33 |
| Melkhior | ), | 17:33 |
| Melkhior | Weird... | 17:33 |
| Melkhior | I need to find a smaller, older micro-sd card than I currently have (https://github.com/sy2002/QNICE-FPGA/blob/master/doc/constraints.txt reports trouble with SPI and modern micro-sd cards...) | 17:36 |
| Melkhior | My attempt at generating litesdcard verilog for inclusion in my (VHDL ;-) ) design: https://gist.github.com/rdolbeau/62a775d4ec5f27575a417ae32eb8a81c | 17:40 |
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| _florent_ | Melkhior: the pinout seems fine, only thing I can see is the un-required PULLUP on the clk pin | 17:56 |
| _florent_ | for now exporting LiteSDCard will indeed not be very easy since there are no generator (as it's the case for LiteDRAM, LiteEth, etc...) | 17:56 |
| Melkhior | tried with and without, doesn't make any difference that I can see ; I'll remove it again | 17:56 |
| Melkhior | (the pullup on clk) | 17:57 |
| _florent_ | maybe try with other SDCard is you have others | 17:57 |
| Melkhior | I tried some designs with alternate cards, same result; unrotunately they are all class-10 UHS1 - I can't find anything older/slower at home... and older/slower cards are as expensive as large, fast ones :-( | 17:58 |
| Melkhior | Anyway thanks for all the help - and for LiteX, quite impressive how it works if you don't deliberately cripple it by using an older, slower mode of operation :-) | 18:01 |
| _florent_ | Melkhior: recent SDCard should work fine, the current limitation is to use ver2.00+ SDCards: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/liblitesdcard/spisdcard.c#L239 | 18:01 |
| _florent_ | Melkhior: BTW, why aren't you able to use the native mode in your application? | 18:02 |
| Melkhior | I can use native mode, but I haven't found a controller that I could integrate with my own design (non-LiteX):-( Everything is either SPI-only (and reasonably easy to use) or a Wishbone-with-DMA-and-all-the-goodies that I can't figure out how to use. I'm trying to interface with another bus, good ol' IEEE 1496-1993, obsoleted in 2000:-) | 18:04 |
| Melkhior | (a.k.a. Sun's own SBus https://github.com/rdolbeau/SBusFPGA) | 18:05 |
| _florent_ | Melkhior: thanks re LiteX, that's really interesting to see what you already manage to do with it (and also the extension you implemented for VexRiscv) | 18:06 |
| _florent_ | ok for your implementation, I remember we discussed this by mail | 18:06 |
| _florent_ | For LiteSDCard, we could eventually work on a core generate together if you want to integrate it as a verilog core in your VHDL design | 18:07 |
| _florent_ | If you want to contribute an initial implementation, I'll be happy to review it and help you getting it working | 18:08 |
| _florent_ | For examples of generators, you can look at LiteDRAM: | 18:08 |
| Melkhior | yep, decided to have a got at it:-) turns out the interface with the SBus worked first time, and I can get some crypto on it :-) | 18:08 |
| Melkhior | Trying to get the sdcard to work turns out to be the big problem - and I was sort of expecting it to be 'standard' enough to be the easiest part... silly me :-) | 18:08 |
| _florent_ | https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py | 18:08 |
| _florent_ | or LiteEth: | 18:08 |
| _florent_ | https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py | 18:09 |
| _florent_ | or LitePCIe :): | 18:09 |
| _florent_ | https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py | 18:09 |
| _florent_ | the aims is always the same, generate a standalone verilog core from a .yml configuration file and the core | 18:10 |
| Melkhior | Oh excellent, didn't realize there were examples:-) | 18:10 |
| Melkhior | I'll look at them and see if I can improve my first poor attempt | 18:10 |
| _florent_ | Melkhior: I think this is really similar to what you did | 18:10 |
| Melkhior | ... and now I'm wondering if I couldn't use litepcie to create a SBus-to-PCIe bridge and solves the peripherals issue once and for all;-) | 18:12 |
| Melkhior | Probably should create a generator for litesdcard and get the d*mn sd card working first, one mad project at a time | 18:13 |
| Melkhior | Thanks again ! | 18:13 |
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