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| joseng | Did anybody use the bitband I2CMaster on an Xilinx/Artix7? Put it in, but only SCL works. For the SDA pad Vivado outputs a waning, that this pad is always driven by constant 0. In the Verilog code, the logic for SDA looks the same as for SCL. I do not understand why Vivado optimizes the SDA logic away. The Tristate condition is driven by the CSR re | 09:21 |
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| joseng | gister, as for SCL. | 09:21 |
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| joseng | Tried now the I2C bitbang implementation from HDMI2USB (https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/gateware/i2c.py), that works. But gives a warning in Vivado "IO port buffering is incomplete: Device port SCL expects both input and output buffering but the buffers are incomplete." | 10:15 |
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| Yam | Hello, I have a quick question. I just recently update litex and found that it's now using vexriscv smp. I'm using linux-on-litex to generate kc705, but it seems to be broken. It seems like vexriscv smp cannot generate litedram interface for 512 bits. Do you have any suggestion of what I should do? Thank you | 12:57 |
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| _florent_ | Yam: are you able to generate the bitstream for the kc705 or is it failing during the VexRiscv-SMP cluster elaboration? | 16:11 |
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| _florent_ | if that's failing during the cluster generation, I would recommend having a look at: https://github.com/enjoy-digital/litex/issues/687 | 16:17 |
| _florent_ | if you are able to build to bitstream but it's not working, you can artificially reduce the dram width with PHYPadsReducer in litex_boards.targets.kc705, similar to: https://github.com/enjoy-digital/litex_vexriscv_smp/blob/master/kc705.py#L82 | 16:18 |
| _florent_ | you can also open an issue on linux-on-litex-vexriscv if you want with the errors you have | 16:20 |
| Yam | Thank you, there is an error from BmbToLiteDram funcition. | 16:24 |
| Yam | I could get it to generate properly if I change the data cache and instruction cache bytePerLine to 128 in VexRiscvSmpCluster.scala But I don't have a board with me to test if the generated bit stream works properly. | 16:25 |
| Yam | I forgot to answer your question. It's failling during VexRiscv-SMP cluster elaboration | 16:34 |
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| oter_ | LiteDRAMDMAReader address translation question: using self.sdram.crossbar.get_port(), I get [on the expix5] port.address_width=25. How do I systematically translate e.g. the 0x40000000 32 bit base of my RAM to the 25 bit address the DMA reader expect? I wonder if I'm missing a bit of magic that does the addr width translation ...? | 21:20 |
| oter_ | the port data_width is 128 bits | 21:27 |
| mithro | joseng: I haven't touched that code in a *very* long time | 21:28 |
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