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| joseng | Hi guys, in all my designs so far with VHDL for xilinx devices I needed to use the inverted clock for the FIFO ports, otherwise lets say the FSM is on the "sys" clock and changes the WE signal of the fifo, the signals would change with the rising edge of the fifo. So when the fifo should latch. This is why I every time used the inverted clock for a | 08:52 |
|---|---|---|
| joseng | FIFO on write and read ports. | 08:52 |
| joseng | But I never saw this anywhere in migen/litex where a FIFO is used. | 08:52 |
| daveshah | There's no need for that. The place and route tooling will ensure that setup/hold times are met | 08:55 |
| daveshah | Using the opposite edge of the clock only serves to reduce the available timing period from one clock cycle to half a clock cycle, and can actually halve Fmax in the worst case scenario | 08:55 |
| joseng | Ah interesting, didn't know that. Thanks | 08:59 |
| _florent_ | daveshah: Hi, I saw on discord you were eventually interested in trying to get LiteSATA running on ECP5, just want to share some info that can be useful I think: | 09:01 |
| _florent_ | I initiated some work recently on that, but only had a few hours to work on this, so there is still work to do | 09:02 |
| _florent_ | I did some test with LiteICLink and the Versa ECP5 at the linerates used for SATA1 and SATA2: 1.5Gbps and 3.0Gbps | 09:02 |
| _florent_ | here: https://github.com/enjoy-digital/liteiclink/tree/master/bench/serdes | 09:02 |
| daveshah | Thanks, thats useful | 09:03 |
| _florent_ | ./versa_ecp5.py --linerate=1.5e9 (or 3.0e9) --build --load | 09:03 |
| _florent_ | sorry | 09:03 |
| _florent_ | ./versa_ecp5.py --linerate=1.5e9 (or 3.0e9) --connector=pcie (or sma) --build --load | 09:04 |
| _florent_ | you can then use a pcie loopback module or sma cable to do the loopback | 09:04 |
| _florent_ | the RX leds should be blinking with the counter generated on TX | 09:04 |
| _florent_ | the PRBS test can also be run with litex_server and ./test_prbs.py | 09:05 |
| _florent_ | I've been able to get 0 errors with the PRBS test, so it shouldn't be too bad | 09:07 |
| _florent_ | but that's possible some adjustments still need to be done on the SerDes parameters | 09:07 |
| _florent_ | I also created a branch in LiteSATA: https://github.com/enjoy-digital/litesata/tree/ecp5 | 09:08 |
| _florent_ | where I started the integration and started working on OOB | 09:08 |
| _florent_ | sata-specification.3.3.gaps-filled-by-sata-qvip_vh-v14-i1.pdf could be useful if you want to understand OOB on SATA | 09:09 |
| _florent_ | I was able to see the COMINIT to see and detect the COMINIT from the device and send the COMWAKE but was not seeing the COMAWAKE from the device | 09:10 |
| daveshah | Great, I'll find some time to give it a try when my ECPIX arrives | 09:10 |
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| _florent_ | daveshah: great | 09:15 |
| daveshah | Being able to capture to a SATA SSD definitely opens up a lot of interesting ideas | 09:16 |
| _florent_ | Indeed, Artix7/Ultrascale(+) support has been added recently, but EPC5 would be really nice | 09:18 |
| _florent_ | For these tests I was using a minimal bench with just the PHY and LiteScope in place: https://github.com/enjoy-digital/litesata/blob/ecp5/bench/versa_ecp5.py | 09:19 |
| _florent_ | I suspect the OOB from the FPGA are not received by the SSD (COMINIT are generated spontaneously by the SSD, even without sending COMRESET) | 09:23 |
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| zyp | ah, ECPIX is available to order now, nice | 10:19 |
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| acathla | Wow, nice board! | 10:41 |
| keesj | seen nice one also? https://shop.lambdaconcept.com/home/46-1-ecpix-5.html#/1-ecpix_5_fpga-ecpix_5_45f | 11:02 |
| tpb | Title: ECPIX-5 (at shop.lambdaconcept.com) | 11:02 |
| zyp | I just ordered one :) | 11:17 |
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| joseng | Am I right in the assumption that the async FIFOs in migen are First Word Fall Through (by default)? Seems to from my tests with it and and watch the output with litescope | 15:03 |
| daveshah | Yes fwft defaults to true | 15:05 |
| daveshah | https://github.com/m-labs/migen/blob/master/migen/genlib/fifo.py#L99 | 15:05 |
| joseng | For the SyncFIFO I saw that there is a parameter, but I mean the AsyncFIFO. Need to cross from the SerDes clock domain to sys | 15:06 |
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| roboknight | Okay, I've gotten the vexrisc running a very short piece of blinky code (not the LedChaser, but some actual software manipulating Leds). I can see the LEDs running. I can even get serial output that I can see. But if I output more than about 16 or so characters, it freezes (no more sweeping LEDs) and no output. | 19:05 |
| roboknight | I was wondering if there might be an issue with multi-level interrupts or something along those lines. | 19:05 |
| roboknight | The ice40-hx8k is VERY small (maybe too small), but I can pack the code in with about 2K ram and about 10K of rom (that nearly exhausts my 32 ram blocks)... I haven't moved to XIP flash yet, but that's where I'm trying to head. | 19:07 |
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| roboknight | I guess I'll stick to UART polling for a while... seems like that works. For now anyway. | 19:23 |
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| joseng | Is there any way to reset/empty FIFOs? | 22:32 |
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| zyp | I don't think so, but I guess it might work with a ResetInserter | 22:38 |
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| joseng | Hmm ok, then I have a look at it, thanks | 23:14 |
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