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| acathla | Does this : [LXTERM] Got unexpected response from device 'b'T'' ring a bell to someone, when trying to serialboot? | 10:13 |
|---|---|---|
| acathla | Last week it was working reaaaally slowly, now it's fast but fails after a few % | 10:14 |
| acathla | at 24% | 10:24 |
| acathla | Ah, the device answers "Timeout" after 37917B sent in one shot | 11:27 |
| keesj | A.... | 11:33 |
| keesj | and now? | 11:33 |
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| Melkhior | acathla I have the issue when serial booting; for me one side or the other of the serial link can't keep up (my serial console is a vintage beaglebone white...) | 12:22 |
| Melkhior | Now my procedure is to | 12:23 |
| Melkhior | a) start the FPGA board with the bitstream | 12:23 |
| Melkhior | b) start the lxterm on the beaglebone | 12:23 |
| Melkhior | (with checksuming enabled) | 12:23 |
| Melkhior | c) do the 'sdram_init' and 'serialboot' by hand | 12:23 |
| Melkhior | If I start lxterm first, it detects the board going up and try to auto-boot, and more often that not if fails with an error similar to yours | 12:24 |
| Melkhior | I know the serial line is problematic as even pasting a full line is enough for some characters to get dropped... | 12:25 |
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| acathla | Hum, thank you Melkhior for sharing your experience. I wonder now what's the right procedure to serialboot... | 12:53 |
| acathla | I use dfu-util -D to send the design to a fomu-like device | 12:53 |
| acathla | then : lxterm --serial-boot --kernel fpga_101__lab004/firmware.bin --speed 115200 /dev/ttyUSB0 | 12:54 |
| acathla | I then got the litex> prompt and type serialboot | 12:54 |
| acathla | oh and I added a --kernel-adr option | 12:55 |
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| Melkhior | @acathla I use a json file to describe the memory mapping, so on my beaglebone: | 14:57 |
| Melkhior | ~/.local/bin/lxterm --speed 1e6 --images boot.json /dev/ttyO4 | 14:57 |
| Melkhior | (the 1Mbit serial line is probably too fast and exlpain the unreliability I experience) | 14:58 |
| Melkhior | The json comes from one of the build (can't remember if it's the bitstream or the buildroot) | 14:59 |
| Melkhior | { "Image": "0x40000000", "rootfs.cpio": "0x40800000", "rv32.dtb": "0x42000000", "emulator.bin": "0x42100000"} | 14:59 |
| Melkhior | I've fixed some stuff compared to default values to fit a largert rootfs | 15:00 |
| Melkhior | (of course some fixes are needed in the binaries as well) | 15:00 |
| Melkhior | if you use linux-on-litex-vexriscv, things should work almost out-of-the-box | 15:01 |
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| acathla | ahah, no linux on the fomu, it's a super tiny FPGA :) | 15:32 |
| Melkhior | I only have experience running Linux ... sorry :-( | 15:50 |
| acathla | using CDC_ACM (USB), it goes to 100% but ends with a CRC error | 16:21 |
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| acathla | If I put a bigger uart fifo I go a CRC error too in serial. | 16:29 |
| acathla | not all the time :( | 16:32 |
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| _florent_ | acathla: we did some changes recently on lxterm to speed up transfers while keeping CRC check | 21:08 |
| _florent_ | acathla: if this was working before, you can try to set sfl_outstanding to 0 here: https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_term.py#L62 | 21:10 |
| acathla | I tried last week and even with --no-crc it was really slow on the uart@115200 and ok on CDC_ACM. | 21:10 |
| acathla | _florent_, what's the meaning of this outstanding? | 21:10 |
| _florent_ | the number of frames allowed to be sent to the FPGA without acks | 21:13 |
| _florent_ | this is used to avoid round trip delays between each frames, so greatly speed up the transfers | 21:14 |
| acathla | ohhh, ok. It works! Well, at least the upload works, now I need to debug the reboot but I think it never worked. | 21:14 |
| acathla | What's the meaning of the cmd reboot? reboot only the CPU, right? | 21:14 |
| _florent_ | this has been discussed here: https://github.com/enjoy-digital/litex/pull/714 | 21:15 |
| _florent_ | it's a reset, before it was only reseting the CPU, but now it's reseting the full SoC | 21:16 |
| acathla | The full SoC but not the FPGA reset, right? Because it seems stuck | 21:18 |
| acathla | I'll look at it tomorrow... | 21:18 |
| _florent_ | You are testing on iCE40/Fomu? | 21:19 |
| _florent_ | I could do a test tomorrow | 21:19 |
| _florent_ | can you try to comment https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L937? | 21:20 |
| acathla | _florent_, it's on a fomu-like hardware | 21:22 |
| _florent_ | if it's no longer stuck, we just need to modify the clocking to add a delay before the reset, I could do it | 21:22 |
| acathla | what do you call the SoCcontroller? | 21:23 |
| acathla | oh, it's a module | 21:24 |
| _florent_ | A small controller with reset CSR, scratch reg CSR, bus error monitoring, etc... | 21:25 |
| _florent_ | acathla: sorry it's the end of the day here :) happy to help tomorrow | 21:25 |
| acathla | okok, bonne soirée :) | 21:26 |
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