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| Krickit | good morning | 08:21 |
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| Krickit | can you explain me what are mem.init, mem_1.init and mem_2.init respectively ? | 08:22 |
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| dkozel | _florent_: The Siglent oscilloscope is a fun new platform! Is there a specific project around that? Seems like a huge amount of work still needed to make that work well. | 11:54 |
| daveshah | It's telling of the kind of volume discounts they must be getting, at retail the FPGA alone would be ΒΌ the price of the scope | 11:56 |
| dkozel | Volume prices on ICs really bend my mind | 12:14 |
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| _florent_ | dkozel: thanks, the pinout is from https://github.com/360nosc0pe and i wanted to see for quite some times if we could run LiteX on it | 12:50 |
| _florent_ | for now the Ethernet/DRAM is working (so already Linux capable) and i'd like to get at least the LCD/Buttons/Leds working and then the ADC | 12:51 |
| _florent_ | some work had already started on that in 360nosc0pe project (it was also LiteX based but only for the peripherals of the Zynq) | 12:52 |
| _florent_ | After that, creating a full standalone scope is indeed a massive work, i'm not planning to work on that, but with just the SoC + ADC support it would be nice to add glscopeclient support | 12:53 |
| dkozel | In a Zynq can LiteX use the hard processor and expose the HDL peripherals to it? | 13:15 |
| daveshah | yeah i think that's what this is for | 13:17 |
| daveshah | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/zynq7000/core.py | 13:17 |
| daveshah | never actually tried it myself tho | 13:17 |
| _florent_ | dkozel: that's indeed the purpose of zynq7000/core.py. I don't use it that much personally but i did for some clients that are running Linux on the Zynq and create the SoC/Peripherals with LiteX. | 13:31 |
| dkozel | So cool. I want a weekend to look at that. Do you have any idea of the max data rate that can be streamed across the interface? | 13:35 |
| dkozel | Have you ever looked at the ADALM PLUTO SDR? | 13:35 |
| _florent_ | dkozel: for the AXI GP we are converting to to AXI Lite when connecing it the main LiteX bus, so that's good for control/status | 13:40 |
| _florent_ | the AXI HP is AXI FULL, so the limitation is the Zynq here | 13:40 |
| _florent_ | I just ordered an ADALM PLUTO a few weeks ago :) but haven't played with it yet. We could add it as a LiteX-Boards platform if you want | 13:43 |
| _florent_ | i also have a simple LiteX AD9631 PHY | 13:45 |
| _florent_ | daveshah: in case you have 2 min, would you mind having a look at: https://github.com/enjoy-digital/litex/pull/696 (ie is passing the idcode of ECP5 12F variant to NextPnr still required?) | 13:48 |
| daveshah | _florent_: no, if you use --12k you don't need the --idcode ecppack param too | 13:48 |
| daveshah | --12k to nextpnr is the recommended route now | 13:48 |
| _florent_ | ok good, that's what we are already doing in LiteX, so the PR is not needed, thanks. | 13:49 |
| daveshah | oops snap we both responded! | 13:54 |
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| _florent_ | daveshah: ah sorry, thanks. | 14:07 |
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| dkozel | _florent_: It would be extremely cool to see even the most basic demo of a LiteX build for the Pluto that has the AD9631 included. | 20:42 |
| dkozel | I was looking at ordering the JTAG adapter for the Pluto, but probably will just solder on some wires | 20:44 |
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| teknoman117 | hello all, I only discovered LiteX recently and have been trying to bring up various components on an Alchitry Au (part: xc7a35t-ftg256-1) I got recently. I'm currently quite stuck with the onboard DDR3. At this point I have it working via Vivado and MIGv7, so I know the module is functional. I mirrored the mimas_a7 target from litex-boards, and I | 21:55 |
| teknoman117 | have some CSR registers I can control via wishbone-tool over a uart (minisoc). I believe I set up my pins correctly (they match the xdc file generated by vivado). However, when I load the gateware, if I write more data via wishbone-tool than the L2 cache is configured for, the older locations just revert to "0". | 21:55 |
| teknoman117 | this is my code so far: https://github.com/teknoman117/alchitry-au-litex/tree/master/ddr3 | 21:56 |
| teknoman117 | the module is a DDR3L module, so I had to add a new module in LiteDRAM with (what I believe) are the correct timings: https://github.com/teknoman117/litedram/commit/42c30dd2ab13a4af515a0890c779a39fd8760d9a | 21:56 |
| teknoman117 | it's the MT41J128M16 module with the tRFC and tRRD timings modified per the datasheet (https://www.alliancememory.com/wp-content/uploads/pdf/ddr3/Alliance%20Memory_2G%20128Mx16%20AS4C128M16D3LB-12BCN%20v1.0%20March%202016.pdf) | 21:58 |
| teknoman117 | the sys_clk_freq was reduced to 83.333 MHz since the -1 speed grade artix-7's can only do 667 Mb/s per pin for DDR3L. (does reducing sys_clk_freq drop the DRAM frequency?) | 21:58 |
| teknoman117 | just looking for some guidance, not really sure where to start debugging | 21:59 |
| daveshah | I'm not really familiar with using wishbone tool instead of an embedded CPU, but do you get some kind of DDR initialisation output? | 22:00 |
| teknoman117 | you know, I haven't tried an embedded cpu at this point (was trying to take baby steps), so if there are initialization steps to start the ddr3 module that's definitely not being done | 22:02 |
| daveshah | Initialisation is definitely required, for example to calibrate the delay primitives and set up the control regs in the RAM | 22:03 |
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| teknoman117 | I switched to using a soft-cpu (this was way too easy lol) | 22:31 |
| teknoman117 | --========== Initialization ============--Initializing SDRAM @0x40000000...Switching SDRAM to software control.Write latency calibration:m0:0 m1:0Read leveling: m0, b0: |00000000000000000000000000000000| delays: - m0, b1: |00000000000000000000000001111111| delays: 28+-03 m0, b2: |00000000000000000000000000000000| delays: - m0, b3: | 22:32 |
| teknoman117 | |00000000000000000000000000000000| delays: - m0, b4: |00000000000000000000000000000000| delays: - m0, b5: |00000000000000000000000000000000| delays: - m0, b6: |00000000000000000000000000000000| delays: - m0, b7: |00000000000000000000000000000000| delays: - best: m0, b01 delays: 28+-03 m1, b0: |00000000000000000000000000000000| delays: - m1, | 22:32 |
| teknoman117 | b1: |00000000000000000000000011111111| delays: 28+-04 m1, b2: |00000000000000000000000000000000| delays: - m1, b3: |00000000000000000000000000000000| delays: - m1, b4: |00000000000000000000000000000000| delays: - m1, b5: |00000000000000000000000000000000| delays: - m1, b6: |00000000000000000000000000000000| delays: - m1, b7: | 22:32 |
| teknoman117 | |00000000000000000000000000000000| delays: - best: m1, b01 delays: 28+-04Switching SDRAM to hardware control.Memtest at 0x40000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiBMemtest OKMemspeed at 0x40000000 (2MiB)... Write speed: 21MiB/s Read speed: 18MiB/s | 22:32 |
| teknoman117 | err, that's not what I intended | 22:32 |
| teknoman117 | I think it works now? | 22:32 |
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| teknoman117 | I got "Memtest OK" | 22:32 |
| daveshah | Yeah that all looks good! | 22:33 |
| teknoman117 | is there any way to use the 1:2 clocking on the Artix-7? If I try to change all the sys4x clocks to something like "sys2x" i get errors about unresolved clock domains | 22:46 |
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