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| a314 | daveshah: yep timing is met, running at 25mhz and nexpnr approves it to 100+mhz | 00:57 |
|---|---|---|
| a314 | having a similar problem now - running with my own wishbone master and CSRs are acting up | 00:58 |
| a314 | if i place a CSR at address 0, it works fine | 00:58 |
| a314 | but if i add a second one at address 0x10, i can't access it | 00:58 |
| a314 | Specifically seems to be the UART CSR that's the problem | 01:08 |
| a314 | guessing it has something to do wit paging (am directly instantiating the CSRBankArray and Interconnect and Wishbone2CSR | 01:11 |
| a314 | but not sure how to fix it | 01:11 |
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| acathla | How is it possible that just one simple comb line takes 194 LC on an iCE40?! | 13:45 |
| acathla | self.comb += self.IR0_phy.rx.rx_enable.eq(~self.IR0_phy.tx.tx_busy | ~self.IR0._conf.fields.echo_cancel) | 13:45 |
| acathla | that's just a sig.eq(~sig1 | ~sig2) | 13:45 |
| daveshah | How are you calculating? | 13:51 |
| acathla | daveshah, I just compare the results given by...yosys I guess, | 13:54 |
| daveshah | Between what though? | 13:54 |
| acathla | with the line and without the line | 13:54 |
| daveshah | That might affect other optimisation decisions | 13:54 |
| acathla | Ok... | 13:55 |
| daveshah | e.g. the self.IR0_phy.tx.tx_busy or self.IR0._conf.fields.echo_cancel logic cones might be removed if nothing else uses them | 13:55 |
| acathla | ok, I'll remove those super expensive registers then... | 13:56 |
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