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| a314 | is there some straightforward way to do verilog builds from LiteX? | 06:55 |
|---|---|---|
| a314 | My specific environment requires me to generate verilog and then feed it into a specific build system, instead of using LiteX's platforms | 06:56 |
| a314 | but it seems that the SoC classes all require a Platform | 06:57 |
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| a314 | Running into a "ERROR: Conflicting init values for signal 1'0 (\basesoc_csr_bankarray_interface2_bank_bus_dat_r [4] = 1'x != 1'0)." when trying to yosys-synthesize a simple LiteX design exported as verilog | 07:56 |
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| daveshah | Is your Yosys up to date? I think a similar bug was fixed a few months ago | 08:30 |
| daveshah | This definitely looks like a Yosys issue rather than a LiteX one either way | 08:30 |
| a314 | 09ecb9b2 | 08:45 |
| a314 | so early july | 08:45 |
| a314 | not sure if that's new enoguh | 08:45 |
| daveshah | I'd try updating that before anything else, just in case | 08:47 |
| _florent_ | a314: you can export yo verilog by creating a generator, similar to: https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_gen.py | 08:50 |
| a314 | daveshah: yeep that fixed it, thanks | 08:51 |
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| a314 | is there any reason why a UARTWishboneBridge would be failing to write but always succeeding on reads? | 21:17 |
| a314 | it takes 3-5 write-sends with wishbone-tool in order to get the value to change | 21:18 |
| a314 | tried with both GPIOOut and SRAM | 21:18 |
| a314 | but reads work perfectly, tried it with GPIOIn and updates effectively immediately | 21:18 |
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