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| disasm[m] | Anyone had an issue when `por` clock domain reset starts driving `sys` clock domain reset and driving conflict emerges in generated verilog? | 10:42 |
|---|---|---|
| disasm[m] | git bisect points to this one: https://github.com/enjoy-digital/litex/commit/2538b2c300f363e0639778422d20af5202b3d012 | 11:10 |
| disasm[m] | Oh well, I see the problem, disregard | 11:14 |
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| lkcl | daveshah, _florent_: the guy who designed the ulx3s ecp5 board says that there' now a "--ecppack" option for uploading to the ECP5 | 13:44 |
| lkcl | compress option to ecppack | 13:44 |
| lkcl | ecppack --compress ulx3s.config --svf ulx3s.svf --bit ulx3s.bit --bootaddr 0 | 13:44 |
| daveshah | --compress, yes, that's been there for a little while now | 13:44 |
| lkcl | he recomm... ah good :) | 13:45 |
| lkcl | i haven't done a git pull for a month or so as we're on a code-freeze for the upcoming dec 2 tapeout | 13:45 |
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