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powergraphic[m] | Hi I'm working on a zynq platform and I was wondering if it is possible to use litex modules with the hard arm core? | 17:25 |
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_florent_ | Hi powergraphic[m], yes it's possible, we don't have lots of examples for this, but you can look at https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/zybo_z7.py | 17:55 |
_florent_ | and https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/zynq7000/core.py | 17:55 |
powergraphic[m] | Great, I will check those out. Thank you. | 17:56 |
powergraphic[m] | I see that the zybo target uses a pregenerated ps7 xci . Will I need to generate that file fror my specific board or is it common to all zync 7000 series. If I need to generate one is there any info on how to do so? | 18:49 |
lkcl | daveshah: oo you have hyperram up and running with litex? | 18:58 |
daveshah | Yes, it is working now | 18:59 |
lkcl | that's fantastic to hear. that's one i really wanted to see in libresoc | 18:59 |
daveshah | Well, thank antti, greg and florent, I was just testing it really | 19:00 |
lkcl | :) | 19:01 |
lkcl | thank you antti, greg and _florent_ :) | 19:01 |
lkcl | which reminds me, has a 16550 uart for litex popped out the woodwork yet, anywhere? | 19:02 |
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