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| _Cactus_ | Hi, I have a very basic question about LiteX do decide its applicability for my uses. I see that all the example cores are contemporary ones, and use contemporary SoC buses. My question is, what about older CPUs that would need to connect directly to RAM and IO port-mapped peripherals? | 10:51 |
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| _Cactus_ | For example, I have my own Intel 8080 core. Would it be feasible to use LiteX to put RAM, ROM and a UART around it to run Tiny BASIC on it? Or are there so many missing pieces of the LiteX puzzle that the juice wouldn't be worth the squeeze and I'm better off just keeping my own bench around it? | 10:53 |
| zyp | I figure it shouldn't be too hard to make an adapter from the memory buses to the main interconnect in litex | 11:25 |
| zyp | I guess you could map the IO bus to part of the memory space as well, but I'm not sure that'd be worth it | 11:28 |
| sorear | I mean, not super familiar with the 8080 but the 8086 has one bus, "is an IO" is effectively an address bit | 11:35 |
| _Cactus_ | zyp: So you're saying my best bet would be to use somethng like Wishbone for all the other parts, and write stuff around my core to connect to that? | 13:15 |
| zyp | _Cactus_, I'd say that depends on what your goal is, and how much benefit you'd have from interacting with other wishbone peripherals | 13:18 |
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| lkcl__ | does anyone know: is there a "non-FPGA" target in litex? a "board that isn't an FPGA"? | 19:16 |
| lkcl__ | i need to create an ASIC, so i need the I/O pins from litex with *no* PLLs, no attempts to connect anything-fancy, just the I/O pins | 19:17 |
| lkcl__ | however of course with all the peripherals, and all the wishbone bus infrastructure | 19:18 |
| lkcl__ | just looking through the list of targets, it *might* actually be the "simple.py" one | 19:20 |
| Finde | it's like the inverse of zynq | 19:49 |
| Finde | in some respects | 19:49 |
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| lkcl__ | Finde: yeah kinda :) | 20:53 |
| lkcl__ | okaay *sigh* i kinda worked it out: i have to create a litex/platforms/name_of_asic.py | 21:01 |
| lkcl__ | which contains the target IO pins, builds some verilog, and that's about it | 21:02 |
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