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| dudeski | I'm new to the Litex / Migen scene. Can anyone tell me how i could generate Verilog for an individual component such as the LiteDram for the Arty, so that i could test it with an existing design? | 00:02 |
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| _florent_ | dudeski: you need to install LiteX: https://github.com/enjoy-digital/litex/wiki/Installation (this will also install LiteDRAM), create a config file for the LiteDRAM generator, ex: https://github.com/enjoy-digital/litedram/blob/master/examples/arty.yml and then do litedram_gen arty.yml | 06:13 |
| tpb | Title: Installation · enjoy-digital/litex Wiki · GitHub (at github.com) | 06:13 |
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| * lkcl__ yippeee! fixed a ton of POWER9 compatibility issues, got a successful litex BIOS boot with LibreSOC | 09:39 | |
| lkcl__ | on the versa ecp5 | 09:39 |
| lkcl__ | abouuut frickin time :) | 09:39 |
| keesj | this boards looks nice to me https://www.xilinx.com/products/boards-and-kits/1-571ww1.html | 09:42 |
| keesj | i likt eh connectors (e.g. not the pmod stuff but something with more connections) | 09:43 |
| SpaceCoaster_ | Ranzbak: the upduino_v1.py platform file has the sb_hfosc instance integrated into the platform.request structure. The v1 doesn’t have an external oscillator so the internal one is used. It is in LiteX-boards. | 09:57 |
| lkcl__ | _florent_, daveshah: thank you for all your help and patience | 09:59 |
| keesj | power9 ? (The revolutionary IBM POWER9 processor chip) ? | 10:00 |
| keesj | https://twitter.com/raptorcompsys/status/1225186761208401920 Check out #Symbiflow...Lattice ECP5 tooling from synthesis to programming the FPGA is 100% open source, supports timing constraints, runs on POWER, and generally does a very good job! | 10:01 |
| lkcl__ | keesj: yes. a POWER9 compliant core. | 10:07 |
| lkcl__ | that's raptor running microwatt which is POWER9. this is libresoc which is also POWER9 | 10:08 |
| sorear | itym Power Architecture V3.00 | 10:25 |
| sorear | for someone very concerned about risc-v trademarks you don't seem to use IBM's carefully | 10:27 |
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| _florent_ | lkcl__: nice you got it working | 15:11 |
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| lkcl__ | sorear: the EULA by IBM says that you can't use the words "POWER9 compliant", and also that open source FPGA implementations have an exemption from needing "Compliance testing" prior to release | 18:32 |
| lkcl__ | someone pointed out that an earlier version of the EULA completely prohibited open source FPGA implementations from being made public until they were properly and fully POWER9 compliant... against a Conformance Test Suite that hasn't even been written yet :) | 18:33 |
| lkcl__ | doh | 18:33 |
| sorear | do they actually call it a EULA | 18:34 |
| lkcl__ | yes | 18:34 |
| lkcl__ | https://www.google.com/search?q=OpenPOWER+EULA | 18:34 |
| tpb | Title: OpenPOWER EULA - Google Search (at www.google.com) | 18:34 |
| sorear | google? i now believe you have been replaced by an imposter | 18:35 |
| lkcl__ | lol sorry :) | 18:35 |
| lkcl__ | byte_select(x) on a signal indexes that byte, right? it's not indexed by bits | 19:20 |
| lkcl__ | i mean word_select | 19:20 |
| lkcl__ | dsel = data_fwd.word_select(i, 8) | 19:22 |
| lkcl__ | comb += data_out.word_select(i, 8).eq(dsel) | 19:22 |
| lkcl__ | ach sorry supposed to be on #nmigen (doh) | 19:22 |
| awordnot | POWER9 is the name of IBM's commercial Power ISA 3.0B implementation and is not licensed for use by any third parties afaik | 20:03 |
| awordnot | the OpenPOWER ISA and associate EULA allow you to say Power ISA compliant, but not POWER9 | 20:03 |
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| awordnot | so really you should call it a Power core or OpenPOWER core, not a POWER{,9} core | 20:04 |
| awordnot | it would be like calling an x86 soft core a Ryzen or i7 | 20:07 |
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