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| Guest1031 | Hi, I am working on adding a new CPU similar to Vexriscv in the core. The cpu description in verilog has been completed but I am stuck at the integration part. I am new to python and I need help for this part. Thanks in advance :) | 09:50 |
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| _florent_ | Hi Guest1031, i want to add a wiki page for this but haven't been found time to write it yet | 10:09 |
| _florent_ | SERV or PicoRV32 are probably easier if you want a simple example of CPU integration: | 10:12 |
| _florent_ | https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/serv | 10:12 |
| tpb | Title: litex/litex/soc/cores/cpu/serv at master · enjoy-digital/litex · GitHub (at github.com) | 10:12 |
| _florent_ | https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/picorv32 | 10:12 |
| tpb | Title: litex/litex/soc/cores/cpu/picorv32 at master · enjoy-digital/litex · GitHub (at github.com) | 10:12 |
| _florent_ | Guest1031: can you describe a little bit more the issue you have? | 10:13 |
| Guest1031 | I do not know how to proceed with the integration part. As of now I am done till the verilog description. I tried to proceed the same way how vexriscv is implemented but no progress was made. | 10:18 |
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| futarisIRCcloud | Coherent DMA looks interesting. Anything that we can use this with? | 13:14 |
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| Guest35327 | For adding the new CPU similar to lm32 or serv, where do I add the verilog file describing the cpu? | 13:26 |
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| somlo | Guest35437: check out https://github.com/litex-hub/pythondata-cpu-lm32 and https://github.com/litex-hub/pythondata-cpu-serv (I'm not familiar with the python magic that connects them starting from e.g. here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/lm32/core.py#L123 | 14:36 |
| tpb | Title: GitHub - litex-hub/pythondata-cpu-lm32: Python module containing verilog files for lm32 cpu (for use with LiteX). (at github.com) | 14:36 |
| somlo | but the litex-hub cpu verilog repos are at the "other end" of the `platform.add_verilog_include_path()` calls | 14:37 |
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