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| mithro | @_florent_: The SymbiFlow toolchain has Zynq support -- we should get that working in a similar manner to the arty version | 03:26 |
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| pepijndevos | How do I exit litex_term? | 08:24 |
| jeanthom | ctrl+c ? | 08:39 |
| pepijndevos | nope | 08:49 |
| daveshah | At one point it was double ctrl+c | 08:49 |
| pepijndevos | lol okay will try, I just killed it now | 08:50 |
| pepijndevos | yeah works | 09:02 |
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| pepijndevos | How can I see what variants are available for a cpu? | 11:45 |
| zyp | not sure there's a way to list it apart from looking in the source | 11:56 |
| zyp | which cpu? | 11:56 |
| pepijndevos | yea, looking at the source now | 11:57 |
| pepijndevos | was mainly looking at vexrisc and picorv32, to match them with the correct Rust tripple | 11:58 |
| _florent_ | mithro: we could had a Zynq target example with Symbiflow, but supporting Symbiflow still requires some workarounds, so that would be good also working on https://github.com/enjoy-digital/litex/issues/554 before adding Symbiflow support to other targets | 11:59 |
| tpb | Title: improve Symbiflow/Arty support · Issue #554 · enjoy-digital/litex · GitHub (at github.com) | 11:59 |
| somlo | _florent_: I'm wrestling with this line: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L848 | 12:02 |
| tpb | Title: litex/soc.py at master · enjoy-digital/litex · GitHub (at github.com) | 12:02 |
| _florent_ | pepijndevos: to exit lxterm, it's ctrl+c two times quickly, this was added to be able to do ctrl+c in the linux shell when linux is running on the FPGA | 12:02 |
| pepijndevos | ewps, when I change the CPU type on ulx3s.py to picorv I get interrupt errors when compiling the bios | 12:03 |
| pepijndevos | undefined reference to `_irq_mask' | 12:03 |
| somlo | if I read the rest of the DMA patch (d38048baa), if the cpu exposes a dma_bus, then the dma masters are connected to the cpu dma slave on a dedicated (separate from the "main" mmio wishbone bus) interconnect | 12:03 |
| somlo | which means that any and all DMA accesses are routed through the cpu's dma_bus slave, either to DRAM, or back out the mmio wishbone "main" bus | 12:04 |
| somlo | which then means that `size` should be (at least) 0x10000_0000 (to cover the whole 4GB physical address space we currently support) | 12:06 |
| somlo | (e.g., rocket has DRAM *starting* at 0x8000_0000) | 12:06 |
| pepijndevos | Can LiteX on ULX3S actually run with picorv32, or is the bios thingy not compatible? | 12:06 |
| _florent_ | pepijndevos: we should indeed improve --help on the targets to provide more useful information, i wanted to revisit things a bit, but haven't been able to work on this yet | 12:08 |
| _florent_ | pepijndevos: but i think if you give a wrong variant, it should give you an error message and list the supported ones | 12:09 |
| pepijndevos | It does actually | 12:09 |
| somlo | _florent_ but if I bump size up beyond 0x8000_0000, vivado craps fails to synthesize with "part-select [29:30] does not match declaration" when trying to access dma_bus_interconnect_shared_adr[29:30] | 12:09 |
| somlo | (unsurprisingly, since it's declared as a "wire [29:0]" somewhere earlier in the generated verilog.... Hmmm, maybe I need to find the corresponding Signal() statement in the migen sources :) | 12:11 |
| _florent_ | pepijndevos: you should be able to run picorv32 on the ULX3S, if not it's broken, could you open a PR? | 12:11 |
| pepijndevos | _florent_, where does this bios stuff live? | 12:14 |
| pepijndevos | ah found it | 12:15 |
| pepijndevos | I think... | 12:15 |
| _florent_ | https://github.com/enjoy-digital/litex/tree/master/litex/soc/software | 12:15 |
| tpb | Title: litex/litex/soc/software at master · enjoy-digital/litex · GitHub (at github.com) | 12:15 |
| pepijndevos | _florent_, https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/picorv32/irq.h externs _irc_mask but apparently it's not there. | 12:19 |
| tpb | Title: litex/irq.h at master · enjoy-digital/litex · GitHub (at github.com) | 12:19 |
| pepijndevos | which seems defined here... https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/picorv32/crt0.S#L304 | 12:20 |
| tpb | Title: litex/crt0.S at master · enjoy-digital/litex · GitHub (at github.com) | 12:20 |
| pepijndevos | is that somehow not getting linked correctly? | 12:21 |
| somlo | _florent_: address width *appears* to come from here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/wishbone.py#L38 | 12:22 |
| tpb | Title: litex/wishbone.py at master · enjoy-digital/litex · GitHub (at github.com) | 12:22 |
| somlo | bumped it up to 32, see if 1. vivado survives the build run and 2. it actually works once built :D | 12:23 |
| somlo | _florent_: looks like vivado won't crap out; testing the bitstream will have to wait though, until I get back from doing chauffeur duty for the family, in a few hours :) | 12:27 |
| pepijndevos | _florent_, issue created https://github.com/enjoy-digital/litex/issues/616 | 12:34 |
| pepijndevos | I'm looking at https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/Makefile#L54 and wondering how crt0.o does (not) get in there | 12:34 |
| tpb | Title: litex/Makefile at master · enjoy-digital/litex · GitHub (at github.com) | 12:34 |
| _florent_ | key2, jeanthom: i saw you were porting LiteDRAM to nMigen in https://github.com/jeanthom/gram, but wouldn't it be better to help us eventually make LiteX work with nMigen in compat mode in a first time if you really want to reuse the LiteDRAM codebase with nMigen? (or generate a standalone controller to verilog which is already possible?) | 12:53 |
| _florent_ | somlo: sorry, i also have the family around and will have difficulties looking at that closely now :), would you mind eventually creating an issue to follow your changes/progress and be able to answer there? | 13:52 |
| pepijndevos | My LiteX core defines rom, sram, csr, and main_ram, what is each typcially used for? | 14:52 |
| somlo | _florent_: sure thing; I'll do that later today; for now, with the modified wishbone interface adr_width and dma_bus region I got it to copy boot.bin to 0x80000000 successfully. It hangs at "liftoff", so there's still some lingering badness, but I think I'm on to something :) | 15:36 |
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| pepijndevos | Why does this version have 32 bit values, while mine has 4 8 bit values? | 16:48 |
| pepijndevos | https://github.com/icebreaker-fpga/icebreaker-litex-examples/blob/a3d1b9d6ded576faf7b299bbd17260ccc6893f66/rust/icebesoc-pac/iCEBESOC.svd#L211 | 16:48 |
| tpb | Title: icebreaker-litex-examples/iCEBESOC.svd at a3d1b9d6ded576faf7b299bbd17260ccc6893f66 · icebreaker-fpga/icebreaker-litex-examples · GitHub (at github.com) | 16:48 |
| pepijndevos | Why is my litex stuck at 0% uploading? | 17:43 |
| pepijndevos | uhhhh. maybe because my binary is 1GB??? | 17:46 |
| daveshah | sounds like a linker script gone wrong | 17:47 |
| daveshah | not seen this with litex before though | 17:47 |
| daveshah | usually it is because it tried to put both ROM and RAM in the binary, and they are at base addresses 1GB apart or whatever | 17:47 |
| pepijndevos | that would be a nice oops | 17:51 |
| zyp | yeah, that's not an uncommon mistake | 18:03 |
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| _florent_ | pepijndevos: it's possible to configure the data-width of the CSR bus (that is used for the registers), for historical we are still using 8-bit as default (thus the 4 8 bit value you see) and the icebreaker design you are linking is probably using --csr-data-width=32 | 18:22 |
| pepijndevos | _florent_, is there a good reason to not use that? | 18:23 |
| _florent_ | somlo: nice, that's already better :) now just need to understand why the data is not valid... | 18:23 |
| _florent_ | pepijndevos: until a few months, some features were still requiring csr-data-with=8, but it's no longer the case now, and we'll switch the default value to 32 soon | 18:24 |
| _florent_ | pepijndevos: so you can use 32 and it will provide better performance. (csr-data-width=8 was initially used to reduce resource usage/improve timing on the CSR bus, but 32-bit seems to work fine even in iCE40 and relatively large designs, so there are no real reason to continue using it). | 18:27 |
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| pepijndevos | okay thanks, I'll try that later. Probably saves a bunch of bit magic | 18:46 |
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| somlo | _florent_: I'll need another hour or so of peace and quiet to dig into it, then I'll post an RFC PR with what I have so far and we can take it from there over the next few days | 18:56 |
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| pepijndevos | Is there any I2C core? | 19:30 |
| sajattack[m] | it's hiding https://github.com/betrusted-io/gateware/tree/master/gateware/i2c | 19:41 |
| tpb | Title: gateware/gateware/i2c at master · betrusted-io/gateware · GitHub (at github.com) | 19:41 |
| pepijndevos | sajattack[m], thanks :) is that just a third party implementation? | 20:10 |
| sajattack[m] | yeah, by bunnie huang | 20:10 |
| pepijndevos | cool cool i'll look at it later | 20:11 |
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| mithro | _florent_: re:SymbiFlow -- I believe many of those issues are fixed already -- the PLL constant one will be shortly | 22:55 |
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