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| futarisIRCcloud | https://twitter.com/Claude1079/status/1275844416083812354 | 00:18 |
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| mithro | Xilinx just published a copy of their Unisim library (normally found in vivado) on GitHub under an Apache 2.0 license! https://github.com/Xilinx/XilinxUnisimLibrary -- next step is to get them to run in iverilog and/or verilator | 01:08 |
| tpb | Title: GitHub - Xilinx/XilinxUnisimLibrary (at github.com) | 01:08 |
| benh | mithro: now if only they also published a VHDL one :-) | 01:17 |
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| benh | _florent_: do that ring a bell | 02:26 |
| benh | LiteDRAM built from Migen b1b2b29 and LiteX 28ea4b3f | 02:26 |
| benh | m0: |000000000000001111111111| delay: 14 | 02:26 |
| benh | m1: |000000000000001111111111| delay: 14 | 02:26 |
| benh | m2: |000000000001111111111111| delay: 11 | 02:26 |
| benh | m3: |000000000011111111111111| delay: 10 | 02:26 |
| benh | (hang) | 02:26 |
| benh | this is standalone microwatt with a litedram generated for Genesys2 (with a 100Mhz sys_clk from the 200Mhz input) | 02:27 |
| benh | using modified version of genesys2.yml from litedram examples | 02:27 |
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| _florent_ | benh: i probably already saw this but was not able to reproduce it easily to investigate. If you are able to easily reproduce it on the Genesys2, can you create a PR on LiteDRAM repo with the required files? i could look at this | 06:53 |
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| benh | _florent_: it's a user trying microwatt standalone with stuff I generated so it's a bit tricky ... there are other weird problems though, some of the stuff the code displays makes no sense (some of my stuff, like it reads some internal config register I have on my wishbone and that seems to return 0 ... but it's hard wired via a generic to some other value and the vivado logs seem to indicate the generic was bound properly ... so a mystery at this point :) | 07:50 |
| benh | _florent_: might be worth asking him to try with LiteX I suppose ... | 07:51 |
| benh | the main difference I noticed is that standalone litedram generates a PLL while LiteX generates an MMCM, the formers has unused "dq" clock outputs but I don't see why any of htat would be a problem (I double checked the configs, they seem fine) | 07:51 |
| benh | oh and LiteX runs at 125Mhz on the genesys while I run at 100 at the moment | 07:52 |
| benh | but I don't have a board to test and investigate myself so ... | 07:52 |
| benh | oh... he didn't wire the cs_n pins of the DRAM in his toplevel ... | 07:52 |
| benh | _florent_: btw, on a different note, you know about FPGAs... :-) | 08:02 |
| benh | _florent_: in microwatt, for historical reasons, we define our wishbones with address bits all the way down to 0 such as the bottom bits are "byte address" and are unused... ie on a 32-bit wishbone we have 2 unused bottom bits and on a 64-bit one, 3 | 08:03 |
| _florent_ | benh: ok for the issue on the Genesys2, just in case there is an easy repro, i have this board so could help | 08:03 |
| benh | _florent_: I've been meaning to clean that up for a while ... so I just did (effectively made all the arrays be N downto 2 or N downto 3) | 08:03 |
| benh | and reduced various latches accordingly | 08:03 |
| benh | and the end result after going through vivado is increased LUT and register utilization | 08:03 |
| benh | can you think of any reason for this ? | 08:04 |
| benh | _florent_: ok thanks. I'll have him try LiteX first and fix a few things in his toplevel | 08:04 |
| benh | _florent_: and if we don't get to the bottom of it, I'll merge his stuff in a branch you can try out if you feel like messing around with standalone mw :) | 08:04 |
| _florent_ | benh: in fact that's probably better to use byte addressing on any buses, this makes integration a lot easier and avoid errors/confusions. The wishbone bus in LiteX uses word addressing for historical reason, but i'm no longer sure it was a good choice | 08:08 |
| _florent_ | benh: that's indeed sometimes difficult to relate logic changes with Vivado's Luts/Register utilization. Very subtles changes can allow it/prevent it to/from optimizing things, the log would need to be carefully analyzed | 08:14 |
| benh | _florent_: thanks. The logs aren't always that clear but yes ... I think I'll leave it as it was then | 08:21 |
| benh | it does make the decoders easier and more readable indeed :) | 08:22 |
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| jaseg | I'm playing around with litex (master) and its vivado backend for artix 7 and vivado fairly frequently crashes ("abnormal program termination" or outright segfaults). Is this expected behavior or is my vivado setup b0rked? | 14:15 |
| jaseg | Simply re-running the same command usually works though. | 14:17 |
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| CarlFK | https://www.ledonlinesale.com/product/colorlight-receiving-card-5a-75b $20ish. | 16:04 |
| tpb | Title: Colorlight Receiving Card 5A-75B - LED Online Sale (at www.ledonlinesale.com) | 16:04 |
| CarlFK | could that drive an LCD over LVDS? (and if so, how about 3 or 4? I think there is enough IO pins | 16:05 |
| _florent_ | jaseg: the issue seems related to your machine or setup, that's not the expected behaviour | 16:13 |
| _florent_ | CarlFK: the colorlight is reversed and supported in LiteX: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/colorlight_5a_75x.py | 16:15 |
| tpb | Title: litex-boards/colorlight_5a_75x.py at master · litex-hub/litex-boards · GitHub (at github.com) | 16:15 |
| _florent_ | @mubes in 1BitSquared#fpga seems to be interesting things with it and LiteX: https://photos.app.goo.gl/ca3tsvYshqLYDPDN6 | 16:16 |
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| CarlFK | _florent_: @mubes in 1BitSquared#fpga seems to be interesting things with it and LiteX: https://photos.app.goo.gl/ca3tsvYshqLYDPDN6 | 18:12 |
| CarlFK | What I am fishing for is using the colorlight board to drive lcd panels like this does https://www.aliexpress.com/item/32955803742.html | 18:13 |
| tpb | Title: PCB800661 Single HDMI Drive Board HDMI to LVDS Adapter Board LCD Screen Drive Plate 7 Inch 42 Inch|Air Conditioner Parts| - AliExpress (at www.aliexpress.com) | 18:13 |
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| lf | CarlFK: i am new to this. but i would say driveing the lvds display should be possoble, but you might need to remove the 5v buffer and add voltage divider to match 3.3 to 1.8V | 18:18 |
| lf | what is the image source HDMI or ethernet? | 18:22 |
| CarlFK[m] | Eathernet. Or rendered by the fpga based on something coming in over ethernet | 18:29 |
| CarlFK[m] | Afk for a while | 18:30 |
| lf | CarlFK: https://twitter.com/Claude1079/status/1232574333308022785 somewhat releated | 18:30 |
| lf | the thread has some infos releated to lvds | 18:30 |
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| satnav | hello everyone, Can someone please suggest me any documentation or tutorial with how to build simple SoC and documentation about the different modules in LiteX? Thanks in advance! | 19:10 |
| zyp | you might want to start out with https://github.com/enjoy-digital/litex/wiki | 19:15 |
| tpb | Title: Home · enjoy-digital/litex Wiki · GitHub (at github.com) | 19:15 |
| satnav | I visited there but most of the topics there are empty / TBD. | 19:17 |
| CarlFK | satnav: this might be a good place to start, https://workshop.fomu.im/en/latest | 19:17 |
| tpb | Title: FPGA Tomu Workshop FPGA Tomu (Fomu) Workshop 0.1-192-ga639335 documentation (at workshop.fomu.im) | 19:17 |
| satnav | thanks zyp and CarlFK! | 19:18 |
| zyp | which board do you have? I personally found the easiest way to be building an existing example for a board I had and then pick it apart to figure out how stuff fit together | 19:21 |
| satnav | I have platform with Lattice ICE40HX1K. it kind of like the "icebreaker" platform. | 19:25 |
| zyp | icestick? | 19:27 |
| satnav | Go board from nandland | 19:28 |
| zyp | ah | 19:29 |
| satnav | I wonder if ICE40HX1K has enough logic to contain RISC-V soft-core (like SERV) and UART. it has 1K LUTs. do you have any experience with ICE40HX1K and LiteX? | 19:31 |
| zyp | I've used litex on the icestick, but without a cpu, haven't checked whether SERV would fit | 19:32 |
| zyp | gonna give it a try :) | 19:34 |
| satnav | nice :) | 19:34 |
| satnav | zyp Do you have the code with LiteX on icestick in GitHub? It will be great to see it | 19:36 |
| zyp | no, it's just a pile of mess :) | 19:42 |
| zyp | I'll upload the serv stuff if I can get it to work | 19:42 |
| satnav | keep update :) | 19:43 |
| zyp | okay, problem 1 is that hx1k only have 8kB of block ram in total, litex bios as it builds requires more | 20:06 |
| zyp | but building without that, it works :) | 20:08 |
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| zyp | https://paste.jvnv.net/view/VaLWq https://paste.jvnv.net/view/aLshV | 20:13 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 20:13 |
| zyp | you can remove the «import deps», that's just some stuff I've got to set up the pythonpath | 20:14 |
| zyp | with --no-compile-software, it builds here, 76% utilization of a hx1k | 20:15 |
| zyp | and then you just need to figure out how to load some software into it :) | 20:16 |
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| satnav | nice zyp! thanks! | 20:17 |
| zyp | SoCCore has an argument called integrated_rom_init, so I guess you could just provide the firmware image there | 20:18 |
| zyp | _florent_ has been talking about making it easier to boot directly into other software than the litex bios, but I'm not sure what the current status of that is | 20:20 |
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| satnav | zyp, can you please tell me what the purpose of CRG module that you have here? https://paste.jvnv.net/view/VaLWq | 22:40 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 22:40 |
| zyp | to instance the PLL to make a 48 MHz clock from the 12 MHz clock input on the icestick | 22:42 |
| zyp | I were experimenting with usb on it, so I needed a 48 MHz clock :) | 22:43 |
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| satnav | thanks (y) | 22:45 |
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