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| somlo | _florent_, benh: got BBL and Linux back and working on 64-bit Rocket (now with exclusively 32-bit aligned CSRs): https://github.com/riscv/riscv-pk/commit/e66bf2e460f1c18916631fb1760415fbd305b8b4 and https://github.com/litex-hub/linux/commit/2a20a88851b4a14c064c1f3a41d7f4b04076ea1a (in https://github.com/gsomlo/riscv-pk/tree/gls-litex-devel and https://github.com/litex-hub/linux/tree/litex-rocket-rebase respectively) | 16:29 |
|---|---|---|
| tpb | Title: LiteX: UART: switch to 32-bit CSR alignment · riscv/riscv-pk@e66bf2e · GitHub (at github.com) | 16:29 |
| somlo | relatively straightforward | 16:29 |
| somlo | now let's have a look at the new linux sdcard driver, see if I can get it working on rocket... | 16:30 |
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| benh | somlo: what would be nice to help further with Linux is an option to fix endianness of CSRs as well | 21:42 |
| somlo | benh: there's a rough equivalent of `include/hw/common.h` here: https://github.com/litex-hub/linux/blob/litex-rocket-rebase/include/linux/litex.h | 22:05 |
| tpb | Title: linux/litex.h at litex-rocket-rebase · litex-hub/linux · GitHub (at github.com) | 22:05 |
| somlo | if all linux drivers used methods as high-level as possible, and they all lived in that file, it'd be very simple to adapt to whatever happens to CSR endianness down the road | 22:06 |
| benh | somlo: well basically if we make CSRs LE always for Linux capable SoCs then drivers just do readl/writel | 22:40 |
| benh | and that's it | 22:40 |
| somlo | bonus points for readq/writeq working transparently across adjacent CSRs through the various up/down shifters and width adapters | 23:03 |
| benh | they should :) | 23:04 |
| benh | at least with my custom downconverter in standalone microwatt but I would expect it to work with the one in LiteX too | 23:05 |
| benh | however, you have to be careful with endian if you do that | 23:05 |
| benh | if it's an actual 64-bit CSR under the hood, it needs to be presented LSB first | 23:05 |
| benh | for LE | 23:05 |
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