Monday, 2020-05-25

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kbeckmann1440p60 would have been fun but it seems I can't go above 800 MHz on the PLL, at least not using the algorithm in ecppll. Maybe it's possible to generate a PLL config that does that anyway :).10:43
zypthe ecp5 pll is specced to a VCO freq between 400-800MHz, so a config generator would naturally try to keep within those bounds to generate a config valid to spec10:51
zypbut if you pick your own factors, nothing prevents you from exceeding that10:53
zypthings will just start acting weid once you get too far out of spec :)10:54
zypweird10:54
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kbeckmannzyp: thanks, I have to try it out. This is already out of spec since the output buffers are rated at 800 MHz and I use them at 1500 (!)14:08
tntMbps not MHz.14:09
zypwhich output buffers? aren't they rated for 400 MHz?14:09
tntyeah 800 Mbps i.e. 400 MHz.14:09
zypI thought top/bottom banks would do 200 and side banks would do 40014:09
zypah, because DDR, right14:10
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loxodesI'm trying to stream samples from an ADC into HyperRAM memory that is attached to a litex soc, do y'all have any advice on how to approach this?17:25
loxodesOn a board with DRAM I've used LiteDRAMDMAWriter to haul samples from a module into memory, but that doesn't support HyperRAM.17:25
loxodesIs there a more general library for streaming data into memory from a module, or should I build something from scrach myself? (I'm inexperienced and mostly work by combining examples, in this case I'd be looking at wishbonebridge for writing to wishbone and LiteDRAMDMAWriter?)17:25
zypnot sure if there are already any stream to wishbone dma modules, but it shouldn't be too hard making one17:41
_florent_loxodes: we don't have a DMA <--> Wishbone currently, but it would indeed be useful for some use cases18:06
loxodesokay, thanks!18:07
_florent_loxodes: creating one similar to LiteDRAMDMAWriter but targeting Wishbone is a good idea, if you want to create it and need help, i'm happy to help18:07
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