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| scanakci | https://www.irccloud.com/pastebin/1AIrGhDw/Recent_Vex_125MhZ | 01:53 |
|---|---|---|
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 01:53 |
| scanakci | _florent_: In a clean vm, I gave a shot to Vexriscv for genesys board using standard flavor. I used the most recent commit. | 01:54 |
| scanakci | Unless something is wrong with my FPGA, I am observing failures | 01:54 |
| scanakci | I will try other frequencies than 125MhZ and see if the behaviour matches with BP | 01:55 |
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| scanakci | I tried 100MhZ for Vex. It prints meaningless characters. I tried a variety of baudrates but no luck. Overall, the behaviour of Vex and BP matches. | 02:22 |
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| _florent_ | scanakci: ok thanks, i'll do a test on a Genesys2 board | 05:51 |
| scanakci | _florent_: thanks. I tried Rocket using 125MhZ. Memory tests failed for it as well. | 06:24 |
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| mattytrentini | OK, I'm finally returning to an old goal - trying to improve MicroPython support on Fomu and, hopefully, for GregD's OrangeCrab. But I've only got a tentative understanding of how the systems hang together. (Maybe I'm in the wrong place; please tell me if there's somewhere else I should be asking these questions!) | 07:24 |
| mattytrentini | Let's say I want to add a standard digital GPIO that I want to be able to access in MicroPython on Fomu. I get that Migen/Litex is responsible for building the gateware including - I think - the VexRiscv softcore for Fomu. How would I go about modifying the softcore to map a pin to the outside world? And then I think I need to provide a way (as a | 07:29 |
| mattytrentini | register on the wishbone bus?) to provide MicroPython with a hook to setting that pin. Finally I need to update MicroPython (currently xobs/MicroPython) to use that hook. Am I even in the ballpark of understanding things correctly? | 07:29 |
| sajattack[m] | sounds about right to me. I'm not sure how to add a gpio in a way linux can see but I'd be curious to know too | 07:33 |
| sajattack[m] | looks like for output you have "leds" https://github.com/litex-hub/linux-on-litex-vexriscv/blob/f96601db3ef6c77a46bd40cc371a4da3c53a295d/soc_linux.py#L105 | 07:34 |
| tpb | Title: linux-on-litex-vexriscv/soc_linux.py at f96601db3ef6c77a46bd40cc371a4da3c53a295d · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 07:34 |
| sajattack[m] | and for input, "switches" | 07:35 |
| sajattack[m] | kinda bodgey though | 07:35 |
| sajattack[m] | the wishbone part should be taken care of | 07:37 |
| sajattack[m] | my guess would be whatever gpio interface in linux raspberry pi uses would be similar to what's used in litex | 07:39 |
| sajattack[m] | since it's on the device tree | 07:39 |
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| mattytrentini | OK, perhaps I can add both an LED and a Switch to have in/out pins... | 08:37 |
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| mithro | mattytrentini: There was a library which could auto-generate MicroPython functions for the registers provided by the FPGA SoC | 13:58 |
| disasm[m] | Hi everyone! I'm looking at the latest litex and now it uses python modules for CPU core sources. Is there a way to declare all the needed python-module dependencies so that my soc generator "just works" as earlier? | 13:59 |
| disasm[m] | (I have been using lxbuildenv.py for maintaining git-deps) | 14:00 |
| mithro | mattytrentini: https://github.com/pazzarpj/micropython-ustubby/tree/34a39f9a9a6421ffb0de57cf37a7d75f71f50dcb#parsing-litex-files | 14:01 |
| tpb | Title: GitHub - pazzarpj/micropython-ustubby at 34a39f9a9a6421ffb0de57cf37a7d75f71f50dcb (at github.com) | 14:01 |
| mithro | disasm[m]: Yes | 14:01 |
| mithro | disasm[m]: xobs posted an example of doing just that somehwere... | 14:03 |
| mithro | https://github.com/enjoy-digital/litex/pull/399#issuecomment-611372489 | 14:05 |
| tpb | Title: Converting LiteX to use Python modules. by mithro · Pull Request #399 · enjoy-digital/litex · GitHub (at github.com) | 14:05 |
| mithro | disasm[m]: > My solution was not to do pip install, but rather cd deps; git submodule add https://github.com/litex-hub/pythondata-software-compiler_rt.git; cd ... | 14:06 |
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| disasm[m] | Thanks! Will try this | 14:08 |
| mithro | https://groups.google.com/d/msgid/linux-litex/90d6adca-fd2c-4e54-85bb-1cc115781cb2%40googlegroups.com - 4 core Linux compatible RISC-V using LiteX on the Digilent Arty A7 35T! -- Only 13k LUTs :-P | 14:10 |
| tpb | Title: Google Groups (at groups.google.com) | 14:10 |
| mithro | disasm[m]: If it would be helpful, you could send a pull request which updates the README.md template with instructions -> https://github.com/litex-hub/pythondata-auto/blob/master/templates/README.md.jinja | 14:11 |
| tpb | Title: pythondata-auto/README.md.jinja at master · litex-hub/pythondata-auto · GitHub (at github.com) | 14:11 |
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| disasm[m] | I kinda love that good old submodule-dependency approach as you can just `git clone --recursive` a project and build it, without any specific pre-installation instructions and custom python environment | 14:15 |
| mithro | disasm[m]: You can actually go even better with git-subtrees | 14:30 |
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| Dolu | Sorry, I miss reported the usage of the SMP quad cores VexRiscv, 13K was when i was testing the cluster itself. With all the required peripherals (DDR, UART, ...) from litex, it is actualy 14762 LUT. | 14:33 |
| mithro | Dolu: So, 8 core? :-P | 14:43 |
| mithro | Dolu: ~13k LUT for the CPU core complex and roughly ~2k LUT for all the support peripherals like DDR / UART / etc? ? | 14:49 |
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| Dolu | mithro: 8 cores, maybe, but not on 35T. Let's do 5 cores on 35T ^^ | 15:00 |
| Dolu | Yes, the cluster itself, is reported as 13433 LUT, while the top (litex) is reported as 1332 LUT | 15:01 |
| Dolu | But will have to see how much the DDR suffer from having so many cores to handle. | 15:03 |
| mithro | Dolu: good thing that we are working on improving litedram's performance! | 15:04 |
| Dolu | yes ^^ | 15:06 |
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| mithro | john_k[m] / Skip: At 15k LUTs for 4 cores, the Pano Logic G2 could have up to like 20 cores! :-P | 16:53 |
| _florent_ | mithro: also for the Pano Logic G2, now that LiteX is supporting SERV, we could use it to have two LiteDRAM standalone core each initialized with a SERV CPU and the VexRiscv SMP in the main SoC would just see the DRAM as a traditional memory already initialized. | 16:58 |
| Skip | _florent_: Speaking about the Pano Logic when you get a chance could you take a look at https://github.com/enjoy-digital/liteeth/issues/38 ? | 17:08 |
| tpb | Title: Error building for Panologic platform ( Spartan 6 xc6slx150) · Issue #38 · enjoy-digital/liteeth · GitHub (at github.com) | 17:08 |
| Skip | mithro: Wow. I wonder how long it will take to route ... one way to find out ! | 17:09 |
| _florent_ | Skip: yes, sure can look at it | 17:21 |
| scanakci | @_florent_, @mithro: Did you test pythondata-cpu-blackparrot to check if modules are properly imported during simulation&synthesis? I am trying to adapt BP to this new form and clean BP repo. | 17:23 |
| scanakci | https://www.irccloud.com/pastebin/QBxLqrPW/ | 17:24 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 17:24 |
| scanakci | The current form is causing errors. Neither manuel setup nor pip worked for me. | 17:24 |
| _florent_ | Skip: which Ethernet PHY are you using on the PanoLogic? | 17:25 |
| Skip | _florent_: It's a Marvell 88E1119R-NNW2 which is almost the same as 88E1111 (https://github.com/tomverbeure/panologic-g2#fpga-external-clocking-architecture) | 17:28 |
| tpb | Title: GitHub - tomverbeure/panologic-g2: Pano Logic G2 Reverse Engineering Project (at github.com) | 17:28 |
| _florent_ | scanakci: i'm not sure we tested it. On my side i was not able to clone the previous submodule correctly: https://github.com/enjoy-digital/litex/issues/391, so haven't been able to test the previous version of BP | 17:28 |
| tpb | Title: Issues · enjoy-digital/litex · GitHub (at github.com) | 17:28 |
| Skip | _florent_: The odd thing about the Pano is that the 125 Mhz clock from the Phy is the ONLY external clock coming into the FPGA and the frequency changes to 25 Mhz when the Phy is reset which is why I made the Phy reset optional. | 17:29 |
| Skip | I wasn't sure what bad things would happen else where if the system clock suddenly changes when the Phy is reset. | 17:30 |
| mithro | scanakci: What is the error? | 17:31 |
| scanakci | https://www.irccloud.com/pastebin/F8XBghNy/ | 17:31 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 17:32 |
| _florent_ | Skip: ok, it's possible the issue is specific to the MII/GMII dynamic mode (we have two clock input going to the BUGMUX since the clock is different in MII and GMII), using a MII or GMII only PHY would probably fix the issue. | 17:32 |
| mithro | scanakci: How are you installing litex? If you are using litex_setup you need to rerun it | 17:32 |
| mithro | scanakci: If you are using a virtualenv or other system, you can use the command it tells you | 17:33 |
| scanakci | BP is not part of litex_setup as far as I see | 17:33 |
| scanakci | I am using litex_setup | 17:33 |
| _florent_ | Skip: BTW, that would be interesting to have the PanoLogic in Litex-Boards: https://github.com/litex-hub/litex-boards | 17:33 |
| tpb | Title: GitHub - litex-hub/litex-boards: LiteX boards files (at github.com) | 17:33 |
| _florent_ | Skip: Would you like to contribute it? | 17:34 |
| scanakci | mithro: I needed to clone it myself based on the README in pythondata-cpu-blackparrot. | 17:34 |
| Skip | _florent_: I'm all for that! I didn't do the port, I just picked up what someone else did and added SPI and Ethernet support. | 17:34 |
| mithro | _florent_: https://github.com/timvideos/litex-buildenv/wiki/HowTo-Linux-on-Pano-Logic-G2 | 17:34 |
| tpb | Title: HowTo Linux on Pano Logic G2 · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 17:34 |
| _florent_ | i also have this board but haven't tested it | 17:34 |
| mithro | Skip: That is where you have been updating things, right? | 17:35 |
| Skip | Yes. I haven't added anything about Ethernet yet. | 17:35 |
| _florent_ | mithro: do you know who has done the original Board support for the PanoLogic (for the copyrights if we put it in LiteX-Boards) | 17:36 |
| mithro | _florent_: Antmicro and kgugala's team | 17:36 |
| Skip | I'll move to a GMII only PHY and if that fixed the build problem I'll send a PR for that. | 17:36 |
| _florent_ | mithro: ok thanks | 17:37 |
| mithro | _florent_: I would just put the "LiteX Authors" | 17:37 |
| Skip | Once the board is in both places how do PRs work? Send in two? One is the "master" ? | 17:38 |
| mithro | _florent_: We should probably go through LiteX and do what this mentions sometime -> https://github.com/SymbiFlow/ideas/issues/47 | 17:38 |
| tpb | Title: Updated the repositories to comply with the current copyright best practices · Issue #47 · SymbiFlow/ideas · GitHub (at github.com) | 17:38 |
| Skip | I've very new to litex... | 17:38 |
| mithro | Skip: We have been slowly trying to move litex-buildenv onto litex-boards but that work isn't finished yet | 17:40 |
| mithro | Skip: Currently there is a lot of duplication between the litex-buildenv/platforms @ timvideos and litex-boards @ litex-hub | 17:41 |
| mithro | Skip: The big thing that was missing was "spi module" information which is being fixed by https://github.com/litex-hub/litespi | 17:41 |
| tpb | Title: GitHub - litex-hub/litespi: Small footprint and configurable SPI core (at github.com) | 17:41 |
| Skip | mithro: Thanks, that helps a lot. | 17:42 |
| mithro | Skip: litex-buildenv has been around a *long* time and it a bit behind the latest "best practices" around LiteX development | 17:43 |
| Skip | That's a good thing. "tried and true" ! | 17:44 |
| _florent_ | mithro: for the copyrights we could discuss it, but i think the current copyrights in LiteX better reflects the contributions than a generic "LiteX Authors". | 17:44 |
| mithro | Skip: We are slowly trying to get rid of and reduce the mishmash of make/shell/python | 17:44 |
| Skip | with Python wining the day I assume? | 17:45 |
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| scanakci | https://www.irccloud.com/pastebin/Hvy1Gyp2/Vexriscv_recent_simulation | 17:59 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 17:59 |
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| scanakci | I just tried simulating Vexriscv using a fresh LiteX repo. It causes errors. | 17:59 |
| scanakci | Rocket gave me the same error. | 18:02 |
| scanakci | mithro: adding blackparrot into litex_setup.py fixed the issue. Import works fine now. | 18:06 |
| mithro | scanakci: What commands did you run? | 18:31 |
| mithro | https://github.com/enjoy-digital/litex#quick-start-guide | 18:32 |
| tpb | Title: GitHub - enjoy-digital/litex: Build your hardware, easily! (at github.com) | 18:32 |
| scanakci | https://www.irccloud.com/pastebin/V7pC1LX9/ | 18:32 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 18:32 |
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| Dolu | scanakci: I think i had the same, i had to install "sudo apt install libevent-dev libjson-c-dev" | 18:44 |
| scanakci | oh my bad. thanks @Dolu, I totally forget dependencies in the fresh vm. | 18:45 |
| Dolu | florent spoted it ^^ | 18:46 |
| scanakci | vexriscv works fine (verilator). | 18:52 |
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| zyp | I'd like to instance a dual ported block ram with differently sized ports, are there any convenient ways to do that, or should I just instance the block ram primitive? | 19:49 |
| zyp | as far as I can see, the Memory class in migen assumes a common width for all ports | 19:50 |
| daveshah | This is a Yosys limitation atm, afaik | 19:51 |
| daveshah | If you are using vendor synthesis tools, I guess the right logic around memory ports might create the Verilog needed to infer an asymmetric RAM, but it's unlikely | 19:51 |
| zyp | if that's the case, I'll just go with the primitive | 19:53 |
| zyp | at the moment I just need it to work on ecp5, can deal with portability later | 19:53 |
| mithro | zyp: are you using litex / migen? | 20:34 |
| zyp | I assumed that was a given since this is #litex :) | 20:36 |
| mithro | zyp: You never know :-) -- It should be pretty easy to create an abstract "DualPortRAM" class which gets instantiated into block rams correctly | 20:37 |
| mithro | zyp: In fact someone might have already done exactly that? | 20:38 |
| mithro | IIRC nmigen has that? | 20:38 |
| mithro | I was wondering if the ASyncFifo has that already | 20:39 |
| mithro | zyp: https://github.com/m-labs/migen/blob/master/migen/fhdl/specials.py#L278 | 20:39 |
| tpb | Title: migen/specials.py at master · m-labs/migen · GitHub (at github.com) | 20:39 |
| zyp | already looked at that | 20:40 |
| mithro | whitequark tends to know a lot about these types of things | 20:40 |
| zyp | 21:50:19 < zyp> as far as I can see, the Memory class in migen assumes a common width for all ports | 20:40 |
| zyp | and if as daveshah says yosys can't infer it correctly anyway, it wouldn't help me much | 20:41 |
| mithro | zyp: I was suggesting that you make the Memory class emit an ECP5 primitive directly rather than trying to make Yosys infer it | 20:42 |
| mithro | mattytrentini: https://github.com/antmicro/litex-micropython-tutorial-pipeline | 20:42 |
| tpb | Title: GitHub - antmicro/litex-micropython-tutorial-pipeline (at github.com) | 20:42 |
| zyp | mithro, ah | 20:43 |
| zyp | but still, the width :) | 20:43 |
| mithro | zyp: https://github.com/m-labs/migen/blob/master/migen/build/xilinx/common.py | 20:44 |
| tpb | Title: migen/common.py at master · m-labs/migen · GitHub (at github.com) | 20:44 |
| mithro | https://github.com/m-labs/migen/blob/5b5e4fdee19c4059b61371c6b70ae927980c24ad/migen/build/xilinx/common.py#L97-L102 | 20:44 |
| tpb | Title: migen/common.py at 5b5e4fdee19c4059b61371c6b70ae927980c24ad · m-labs/migen · GitHub (at github.com) | 20:44 |
| mithro | zyp: That should show you how to provide an override for a specific platform | 20:46 |
| zyp | fair enough | 20:46 |
| mithro | zyp: Assuming you want to go the "generic dual port block ram" approach | 20:47 |
| zyp | but I really don't want to spend a ton of time on this right now, I just want a memory so that I can work on the interesting stuff that hooks up to the memory | 20:47 |
| mithro | zyp: Then just use this -> https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers#instances | 20:49 |
| tpb | Title: LiteX for Hardware Engineers · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 20:49 |
| zyp | long term I might replace the whole thing with an arbiter on a single port memory | 20:49 |
| zyp | yeah, I'm already in the middle of hooking it up | 20:49 |
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| zyp | https://paste.jvnv.net/view/gQZvi <- ending up with something like this | 21:11 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 21:11 |
| daveshah | This isn't correct, CSA/B are chip selects for large memories not byte enables | 21:17 |
| daveshah | The lowest two address bits are the byte enables | 21:17 |
| daveshah | See https://github.com/YosysHQ/yosys/blob/master/techlibs/ecp5/brams_connect.py#L54 | 21:18 |
| tpb | Title: yosys/brams_connect.py at master · YosysHQ/yosys · GitHub (at github.com) | 21:18 |
| daveshah | Also note if you want wider than 18 bits you need to use PDPW16KD which is only pseudo dual port | 21:19 |
| zyp | oh, right, I read too fast on the cascading ports, thanks for spotting that | 21:20 |
| daveshah | I'm not sure if it is required, but tying the CE and OCE ports to 1 and RST to 0 is a good idea too | 21:22 |
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| zyp | daveshah, so if I'm understanding this correctly, the active address lines are always the upper ones, and then the lower two or four bits are the byte lane enables for 18b and 36b wide ports, right? | 21:44 |
| zyp | in the file you linked, why does only line 54 have the EN signal, not line 55? (and correspondingly for line 61/62) | 21:45 |
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