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| shuffle2 | in ecp5rgmii, LiteEthPHYRGMIICRG does self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk); is that..normal? | 02:56 |
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| mithro | xobs / bunnie: Did I ever share https://github.com/timvideos/litex-buildenv/wiki/HowTo-HDMI2PCIe-on-NeTV2 with you? | 04:27 |
| tpb | Title: HowTo HDMI2PCIe on NeTV2 · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 04:27 |
| xobs | mithro: I don't think so! | 04:28 |
| xobs | PCI makes me nervous. I always think of it as some super fragile thing, but I gather that's not the case. | 04:29 |
| xobs | On Novena, if you even looked at it funny the whole system would lock up. But I bet that's just because of bugs in the Synopsis IP. | 04:29 |
| xobs | On x86, does your whole system lock up if you reset the PCIe card? | 04:29 |
| mithro | xobs: I'm pretty sure you attended that talk from your failoverflow friend who did that horrible PCIe over uart on the PS?4? system? | 04:30 |
| mithro | xobs: https://news.ycombinator.com/item?id=20402131 | 04:30 |
| tpb | Title: Ive seen pcie literally run over a metal clothes hanger soldered to the board. ... | Hacker News (at news.ycombinator.com) | 04:30 |
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| xobs | True, but I think most of the bugs and lockups I encountered were during enumeration. | 04:31 |
| xobs | Basically, how fidlly is it? Do you need to restart the host every time you redo the firmawre on the device? | 04:31 |
| mithro | xobs: No idea, I haven't actually tested it :-P | 04:32 |
| xobs | I see. | 04:34 |
| mithro | kgugala: Might know | 04:34 |
| xobs | Still, if I had access to a machine with one of those in there running a gateware with a wishbone bridge, I don't think it would be too difficult to add support for it in `wishbone-tool`. | 04:34 |
| mithro | I know they were struggling with the buffer allocation and DMA pointer updates | 04:34 |
| mithro | (Getting tearing and something around color?) | 04:35 |
| xobs | The problem is I only have a few machines with PCIe slots, and they don't really like being turned off or rebooted. | 04:35 |
| mithro | xobs: I have a bunch of turbots sitting here waiting for me to set them up for exactly that | 04:35 |
| xobs | (I have enough troubles with this DVB-T2 USB card causing KPs whenever it's disconnected.) | 04:35 |
| john_k[m] | I just put up a litex PR to add a concept of an SDK for the generated SoC, that is a standalone set of headers, makefile fragments, and binaries to enable building firmware for the generated SoC without relying on litex internals. This came from a conversation with Mubes on 1BitSquared Discord. (https://github.com/enjoy-digital/litex/pull/487) | 05:11 |
| tpb | Title: litex/soc/integration: Add SDK output directory by John-K · Pull Request #487 · enjoy-digital/litex · GitHub (at github.com) | 05:11 |
| john_k[m] | Would love feedback / pointers on how to do this better | 05:11 |
| _florent_ | xobs: PCIe is quite reliable and not that complicated, the only thing that is not very convenient during dev is that you have to reboot the machine when reloading the bitstream for the enumeration, but on Linux it seems possible to do a PCIe rescan (but haven't spend the time to get it work) and when passing through thunderbolt (card in an expansion chassis) it automatically re-enumerate. | 05:19 |
| _florent_ | xobs: i could give you remote access to a NeTV2 board connected to a Host through PCIe if you want to do some wishbone-tool tests | 05:20 |
| _florent_ | xobs: you just have to do a MMAP of the BAR0 to access the main bus of the SoC: https://github.com/enjoy-digital/litex/blob/master/litex/tools/remote/comm_pcie.py | 05:21 |
| tpb | Title: litex/comm_pcie.py at master · enjoy-digital/litex · GitHub (at github.com) | 05:21 |
| xobs | _florent_: that's the code I was going off of! Is all of Wishbone mapped there? Is it a 4gb file? | 05:26 |
| _florent_ | john_k[m]: thanks john_k[m], i will look at that. I think @esden, @xobs, @bunnie could also be interested by that since are replacing the BIOS with custom firmware and use LiteX to generate just the gateware/headers. | 05:27 |
| john_k[m] | Cool, thanks _florent_ | 05:28 |
| _florent_ | xobs: on most of the systems, i'm only exposing the CSR region, so with a reduced BAR0 size and CSR region mapped to address 0. But we could use a larger BAR0, the larger i tested was 512MB, but it could probably be increased. | 05:31 |
| xobs | I see. Is that offset exposed anywhere in the csr.csv file anywhere? | 05:35 |
| xobs | Or maybe we could make it a banked window. | 05:36 |
| xobs | For example, there's a Wishbone command to jam a file into ram. | 05:36 |
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| _florent_ | xobs: we can retrieve this information from the .csv file yes. | 07:20 |
| _florent_ | daveshah: from your write leveling results, it seems there is a large delay difference on the clk/cmd between modules 0-3 and modules 4-8, not sure this a situation i already encountered, maybe we should handle it by allowing dynamic cmd latency and allow the software to test different cmd_latency for each byte. I could investigate that when i'll reveice a similar board. | 07:25 |
| daveshah | Makes sense | 07:29 |
| _florent_ | daveshah: in case you think you are not going to modify your changes, could you create a PR for the different changes? This will allow starting integrating them and going further. | 07:29 |
| daveshah | They need tidying up first, but I will do | 07:30 |
| daveshah | (in particular making the RDIMM stuff conditional on an RDIMM being used) | 07:30 |
| _florent_ | daveshah: ok perfect, thanks. | 07:31 |
| _florent_ | while the issue is not fixed, if you need the DRAM you could probably restrict LiteDRAM to only use half of the modules, i could add a function to ease that as we discussed. | 07:33 |
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| daveshah | I might also experiment trying different channels, if the difference is due to routing on the board rather than the DIMM | 08:18 |
| _florent_ | daveshah: https://github.com/enjoy-digital/litedram/commit/9a2d3f0eb9ae059077db6972f362f02b5d4a6a4e if this is not useful for you now, it will be for me in the future :) | 08:36 |
| tpb | Title: common: add PHYPadsReducer to only use specific DRAM modules. · enjoy-digital/litedram@9a2d3f0 · GitHub (at github.com) | 08:36 |
| daveshah | Thanks! I can also re-enable all 72 bits now too | 08:36 |
| daveshah | This won't work for the U250 as is though, because it is using x4 DQS | 08:37 |
| _florent_ | daveshah: yes i was thinking about that | 08:37 |
| _florent_ | daveshah: we could add more parameters to support it | 08:38 |
| daveshah | On the phy side for now I added a x4_dimm_mode that disables DM and duplicates DQS (currently using the same delay for both nibbles in a byte which seems to work here, but might need to be changed to per nibble control for other boards) | 08:40 |
| _florent_ | ok, in fact we could also probably avoid the parameter (for the PHY and PHYPadsReducer too) by looking at the len(pads.dq)/len(pads.dqs) ratio | 08:41 |
| daveshah | Oh yeah, that makes sense | 08:42 |
| daveshah | I guess we could just disable DM if the pads aren't present, too | 08:42 |
| _florent_ | x4_dimm_mode = (len(pads.dq)/len(pads.dqs) == 4) | 08:42 |
| _florent_ | you we could do that for DM, that's what we are doing in GENSDRPHY IIRC | 08:43 |
| daveshah | _florent_: how should "this is an RDIMM" and the RDIMM configuration (which needs to include the clock frequency) be passed to get_sdram_phy_init_sequence ? | 09:04 |
| _florent_ | we should probably add that to the phy_settings | 09:22 |
| scanakci | how can I undefine a MACRO used in multiple files in soc/software? CONFIG_CPU_HAS_INTERRUPT is defined by default and I need to undef it (potentially modifying genesys.py) | 09:24 |
| _florent_ | scanakci: you want to avoid interrupts with blackparrot right? | 09:25 |
| scanakci | yeah, I am using polling not external interrupts | 09:25 |
| _florent_ | this flag is generated if you have an interrupt signal on your CPU wrapper: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L787-L790 | 09:28 |
| tpb | Title: litex/soc.py at master · enjoy-digital/litex · GitHub (at github.com) | 09:28 |
| _florent_ | and UART_POLLING mode is now automatically selected if your CPU does not manage interrupts: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L980-L983 | 09:29 |
| tpb | Title: litex/soc.py at master · enjoy-digital/litex · GitHub (at github.com) | 09:29 |
| scanakci | I see. Thank you. | 09:29 |
| _florent_ | so if you are not using the interrupts, you can remove the interrupt signal of the CPU wrapper, it will automatically switch to UART_POLLING | 09:29 |
| daveshah | _florent_: I've created a PR for the x4 support and adding the module, I'll need to spend a bit longer on the RDIMM init | 09:49 |
| _florent_ | daveshah: ok thanks, i'll look at these PRs. | 09:52 |
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| zyp | hmm, I assume the litex bios uses the rom and sram regions, so that if I want to serialboot my own code, I either need to load it into main_ram or add a second sram area for it? | 10:22 |
| _florent_ | zyp: indeed, you can do something like this: https://github.com/enjoy-digital/litedram_init_test and add the ram with: self.add_ram("firmware_ram", 0x20000000, 0x8000) | 10:24 |
| tpb | Title: GitHub - enjoy-digital/litedram_init_test: Example of LiteDRAM initialization with a firmware in RAM loaded via serialboot. (at github.com) | 10:24 |
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| zyp | how does interrupts work? I'm used to there being a vector table at the beginning of the image | 10:28 |
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| _florent_ | zyp: it will be specific you the CPU arch you are using, the gateware is just doing to connection between the irqs of the peripherals and CPU, for the software, you could look at https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/include/base/irq.h | 10:35 |
| tpb | Title: litex/irq.h at master · enjoy-digital/litex · GitHub (at github.com) | 10:35 |
| _florent_ | and the crt0 in https://github.com/enjoy-digital/litex/tree/master/litex/soc/software/libbase | 10:35 |
| tpb | Title: litex/litex/soc/software/libbase at master · enjoy-digital/litex · GitHub (at github.com) | 10:35 |
| xobs | _florent_: if you want to set up a server so I can add pcie support, I can try that tomorrow. | 10:37 |
| zyp | _florent_, thanks, I'll have a look | 10:39 |
| _florent_ | xobs: ok great, i'll prepare that this afternoon | 10:40 |
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| john_k[m] | mithro: re SDK PR, shipping the output directory isn’t sufficient as many headers and a makefile fragment live in the Litex source tree. The goal here is to have a release artifact (eventually including docs) that can be distributed alongside gateware so end users can develop firmware for the SoC without needing to care about Litex/FPGA toolchains/python modules | 19:05 |
| shuffle2 | i have some existing verilog code that generates a stream of data, and i'm trying to send it out via LiteEthUDPIPCore. the stream is variable length data | 19:14 |
| shuffle2 | so i've wrapped it in stream.Endpoint, assigned .valid and .last, and UDP sends the appropriate data content + length | 19:15 |
| shuffle2 | however the udp size field is not set correctly | 19:15 |
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| shuffle2 | should I be using Packetizer? i need to decode the beginning of the stream to figure out packet length. doing this myself and then assigning .length of the eth_udp_user_description still results in 0 data size in udp header. so i assume LiteEthUDPTX requires length to be set at packet start and i'm missing the window? | 19:17 |
| shuffle2 | buy just from looking at the python i dont really get where the issue is :/ | 19:18 |
| shuffle2 | but* | 19:19 |
| mithro | john_k[m]: Do you mean the libcompiler_rt stuff? | 19:32 |
| mithro | john_k[m]: We should really be pushing people developing their own firmware to be using newlib or similar? | 19:40 |
| john_k[m] | all of the headers from `litex/soc/software/include/` and `common.mak` | 19:44 |
| zyp | I'm about to start adding riscv support to my arm mcu hardware abstraction lib, I'm planning to just ingest the csr.csv/json and generate my own headers from that | 19:44 |
| john_k[m] | maybe for some larger projects, sure | 19:45 |
| mithro | john_k[m]: I would say pretty much everything under the `include` directory should potentially go away | 19:46 |
| john_k[m] | hrm, interesting | 19:46 |
| mithro | john_k[m]: I do think you are potentially going in the right direction in that everything under the build directory should be what is needed to use the fpga | 19:48 |
| john_k[m] | I guess that all makes sense, I think the goal here was just to reduce barriers to getting things started. | 19:48 |
| mithro | john_k[m]: Yeap! Maybe it makes sense to land something like this temporarily with a goal of deleting it in the future? | 19:49 |
| john_k[m] | I had to look at a few different examples: esden's icebreaker-examples and litex-hub's fpga-101 to figure out how to get started with my first firmware project - would be great if litex made that easier | 19:50 |
| john_k[m] | maybe? could be an ecosystem bootstrapping thing? | 19:50 |
| mithro | john_k[m]: So, I'm not suggesting that we /can't/ merge this pull request - just trying to give you some more context or other potential ideas | 19:51 |
| john_k[m] | yep, I didn't take it that way - like I said, just wanted to spark some conversation here and try to figure out how to make getting started easier and for people writing FW | 19:52 |
| john_k[m] | would be open to helping on the libc front as well | 19:52 |
| mithro | john_k[m]: It's been on our todo list for a long time -- the primary thing blocking it is the LTO support | 19:55 |
| john_k[m] | LTO support in what part? | 19:56 |
| john_k[m] | does gcc not support it yet? It looks like LTO for clang / riscv was added in v10.0 | 19:59 |
| mithro | Link time optimization | 20:03 |
| john_k[m] | yep, that's what I assumed you were referring to - what's the roadblock? | 20:04 |
| mithro | john_k[m]: https://github.com/enjoy-digital/litex/pull/401 | 20:06 |
| tpb | Title: software: enable link time optimization (LTO) by mateusz-holenko · Pull Request #401 · enjoy-digital/litex · GitHub (at github.com) | 20:06 |
| mithro | john_k[m]: But it was revert | 20:06 |
| mithro | mateusz-holenko knows the current status (and works for kgugala) | 20:06 |
| john_k[m] | aha, thanks I'll read up on it | 20:14 |
| shuffle2 | i guess i need to setup this litescope thing over uart to try and figure out what's wrong? :( | 20:15 |
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| shuffle2 | is there some actual expectation about how you should (or should not) drive and Endpoint's first/valid/last/etc? | 20:39 |
| shuffle2 | an* | 20:39 |
| shuffle2 | i created a udp crossbar with datawidth=16 and udp logic is somewhere byteswapping the data :| | 21:00 |
| shuffle2 | crossbar port* | 21:00 |
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| dkozel | Ha, hi xobs I'll test out your Rust code in the next two days. | 22:04 |
| dkozel | ah, and I see florent is going to setup a server. If for whatever reason that doesn't work out I can DM you access to a live environment here with a PCIe card | 22:09 |
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