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| gregdavill | Are there any examples of adding a second CSRBank to a SoC? | 01:40 |
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| gregdavill | I think I've got it working correctly, but now I'm wanting to tidy up the implementation. | 01:41 |
| gregdavill | I'm essentially creating a new CSR bus, and passing the address/data signals through a clock domain via an AsyncFIFO. | 01:43 |
| gregdavill | This is specifically for operating valentyusb.eptri 12MHz, from a CPU that's running at 48-72MHz. | 01:44 |
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| _florent_ | gregdavill: for second CSRBank, you have to do it manually for now, probably as you just did. The potential issue with CSR and CDC is that the CSR is expecting reads to be returned on the next clock cycle which is not possible if the origin clock is faster than the target clock. Doing CDC on Wishbone would be possible (due to the stb/ack) but not currently implemented in LiteX. | 07:42 |
| _florent_ | gregdavill: happy to have a look at your implementation to see if we could ease this in LiteX | 07:43 |
| gregdavill | I've created a custom WB2CSR. Which exposes an Ack signal that is fed externally if a read is performed. | 07:53 |
| gregdavill | Essentially I send Addr/Dat/we signals through an Async FIFO, and then if we is low, addr/dat is sent back though another AsyncFIFO. Ack is esserted when the address back matches the pending request. | 07:55 |
| gregdavill | I'm trying to just have all the cdc stuff happening at the CSR bus, because it's nice and simple. But I've had to tie in a wishbone level to hold the CPU to handle reads. | 07:56 |
| gregdavill | This way isn't super fast for reads, but uses the least amount of resources. | 07:58 |
| zyp | does the link part of valentyusb really have to be operated at 12MHz? | 08:10 |
| zyp | I'm currently working on a usb core of my own, and while the phy needs to operate at 48 MHz, the link should be able to operate at whatever as long as it's able to keep up | 08:11 |
| _florent_ | gregdavill: ok i see, it's indeed complicated to do CDC on CSR due to the assumption data should be ready on the next cycle | 08:19 |
| _florent_ | In the future, we should probably allow creating different groups of CSRs running in different clock domains and let the tools connect it to the main bus and insert the CDC modules. But not sure this is going to be very soon, so your solution is probably fine for now. | 08:23 |
| _florent_ | zyp: i'm not well aware of valentyusb, but the link is probably working at 12MHz to simplify CDC between 12MHz and 48MHz and reduce resource usage. | 08:26 |
| zyp | https://github.com/im-tomu/valentyusb/blob/master/valentyusb/usbcore/rx/pipeline.py#L104 <- it's using an AsyncFIFO for CDC and my understanding is that that should work for arbitrary clock differences, am I mistaken? | 08:29 |
| tpb | Title: valentyusb/pipeline.py at master · im-tomu/valentyusb · GitHub (at github.com) | 08:29 |
| zyp | ah, looks like the tx pipeline is running the serializer from the 12MHz clock | 08:34 |
| gregdavill | I actually haven't looked into it too deeply, I just assumed that the 12/48MHz domains were quite tightly coupled. | 08:48 |
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| btashton | I'm trying top build the kernel module for the litepcie core, but I am a little unclear as to how I should be integrating this with the generated sources from my litex build | 18:36 |
| btashton | I see I was not generating the correct headers. | 18:56 |
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| scanakci | https://usercontent.irccloud-cdn.com/file/qJzHynYT/BlackParrot-Litex%20Linux | 21:06 |
| scanakci | I could simulate Linux on Litex for BlackParrot. | 21:06 |
| scanakci | @_florent_: There were some issues on BlackParrot side. I will resolve the issues once I could run Linux on FPGA. | 21:07 |
| scanakci | I am expecting to make it happen this week. | 21:07 |
| somlo | scanakci: nice! How long did it take to boot Linux in the simulator? | 21:16 |
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| Skip | I'm trying to get Linux running on my Panologic G2, but I get a build error with the current tree: | 22:21 |
| Skip | When I build the gateware for the default CPU_VARIANT it builds and runs, but when I set CPU_VARIANT to linux the build fails with: | 22:22 |
| Skip | File "/home/skip/pano/working/litex-buildenv/targets/pano_logic_g2/base.py", line 86, in __init__ | 22:22 |
| Skip | anyone had any ideas? | 22:22 |
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