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| SingularitySurf | Hi, could someone give me a hint on how I can add my own code to the BIOS to set up some custom peripherals? | 10:14 |
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| acathla | https://github.com/enjoy-digital/litex/wiki/Create-And-Load-Software-To-The-CPU | 13:07 |
| tpb | Title: Create And Load Software To The CPU · enjoy-digital/litex Wiki · GitHub (at github.com) | 13:07 |
| acathla | it's empty, so yeah, how do I add the bios/program to the .bit file on a spartan6? | 13:09 |
| acathla | ISE complain : INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER). | 13:09 |
| acathla | 9K Block RAM initialization data, both user defined and default, requires a | 13:09 |
| acathla | special bit stream format. | 13:09 |
| acathla | Hum, I have a litex> prompt, may be it's ok finaly | 13:13 |
| _florent_ | acathla: yes it's still empty, i created the topics and try to fill things progressively :) | 13:31 |
| acathla | Bon courage! | 13:31 |
| _florent_ | :), this can be useful to create a custom firmware and load if to the CPU: https://github.com/litex-hub/fpga_101/tree/master/lab004 | 13:33 |
| tpb | Title: fpga_101/lab004 at master · litex-hub/fpga_101 · GitHub (at github.com) | 13:33 |
| _florent_ | There is also this: https://github.com/enjoy-digital/litex/wiki/Tutorials-Resources | 13:34 |
| tpb | Title: Tutorials Resources · enjoy-digital/litex Wiki · GitHub (at github.com) | 13:34 |
| somlo | _florent_: I've managed to patch litex_soc_ctrl for 64bit, then liteeth and litespi to work on 64bit with litex_soc_ctrl (https://github.com/gsomlo/linux/tree/litex-devel-next) | 13:48 |
| tpb | Title: GitHub - gsomlo/linux at litex-devel-next (at github.com) | 13:48 |
| somlo | I then built a kernel with litespi *and* CONFIG_MMC_SPI=y | 13:49 |
| somlo | but now I am stuck at coming up with the right DT node description | 13:49 |
| _florent_ | somlo: nice, sorry i saw your previous progress but haven't answered yet | 13:52 |
| somlo | I can do a straightforward "litespi0" node and see the probe function succeed. But setting up a "mmc-spi-slot" on top of that is s | 13:53 |
| somlo | *is still a mystery :) | 13:53 |
| _florent_ | somlo: i think you just need to replace the spidev0 part in the dts: https://hastebin.com/konisemomo.makefile | 14:22 |
| tpb | Title: hastebin (at hastebin.com) | 14:22 |
| somlo | _florent_: https://hastebin.com/isomukivub.xml | 14:37 |
| tpb | Title: hastebin (at hastebin.com) | 14:37 |
| somlo | maybe I still need to add something to the kernel config (besides SPI, SPI_MASTER, SPI_LITESPI, and MMC_SPI)? | 14:38 |
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| _florent_ | somlo: sorry, not sure i explained it correctly, i think you need something like this: | 14:42 |
| _florent_ | https://hastebin.com/belajicuse.py | 14:42 |
| tpb | Title: hastebin (at hastebin.com) | 14:42 |
| _florent_ | (sorry for the python part, i'm editing json2dts.py) | 14:42 |
| fkokosinski | _florent_hi, i've been trying to reproduce some working setup with litevideo in ycbcr mode. I've tried your https://github.com/enjoy-digital/netv2 design on netv2 board and got this from pattern fb: https://drive.google.com/file/d/1XSO7sElsx-UMvwVAsV6Rp32STnQNCrod/view?usp=sharing. In firmware's source code it states that the white, yellow, cyan, | 14:43 |
| fkokosinski | green and so on, so they don't really match. Did it use to be like this when you worked on it, or maybe some recen change to one of the litex cores caused this behavior? | 14:43 |
| tpb | Title: GitHub - enjoy-digital/netv2: NeTV2 SoC based on LiteX (at github.com) | 14:43 |
| somlo | _florent_: oooh, embed the mmc-slot thing *within* litespi0 | 14:44 |
| somlo | let me try that :) | 14:44 |
| somlo | _florent_: progress! https://imgur.com/a/7hPahcF | 14:54 |
| tpb | Title: Imgur: The magic of the Internet (at imgur.com) | 14:54 |
| somlo | now I need to figure out what "unsupported mode bits 4" and "can't change chip-select polarity" actually means, but this is way better than the sound of crickets I was experiencing before :D | 14:55 |
| _florent_ | somlo: ok good :) | 14:59 |
| _florent_ | somlo: i'm also going to do some tests on the nexys4ddr with Linux-on-LiteX-Vexriscv | 15:05 |
| somlo | _florent_: and (obviously) thanks for getting me unstuck w.r.t. the DT entry! I'll pick this back up later in the afternoon (got some $DAYJOB stuff I kinda have to take care of first) :) | 15:09 |
| fkokosinski | _florent_ ping | 15:49 |
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| mithro | somlo: Is Rocket verilog of systemverilog? | 16:22 |
| somlo | mithro: litex-data-cpu-rocket/... is Verilog (upstream Rocket sources are Chisel) | 16:27 |
| mithro | somlo: Thanks, I think I was getting it confused with Ariane | 16:28 |
| somlo | I thought Ariane was also Verilog (not *System*), but don't quote me on that :) | 16:29 |
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| somlo | _florent_: is the `reg = <x>` value of `mmc-slot@x` relative to that of the enveloping `spi@yyy`, or is it absolute (i.e., x == yyy)? | 16:49 |
| Finde | ariane is sv fwiw | 17:40 |
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| somlo | _florent_: after some RTFMing, it appears nested nodes' `reg` properties are relative to their parents', so if litespi starts at 0x12004800, and the mmc-slot nested inside should also start at 0x12004800, the latter really *does* need to have `reg = <0>`, i.e. start at parent node's offset | 18:46 |
| somlo | at least one fewer things to confuse me :) | 18:47 |
| mithro | _florent_: I'm a bit confused about how the build at https://travis-ci.com/github/enjoy-digital/litex/jobs/315546886 succeeded, given it downloaded a Linux binary on Mac? Is the compiler never actually used as part of the setup.py test command? | 19:35 |
| tpb | Title: Travis CI - Test and Deploy with Confidence (at travis-ci.com) | 19:35 |
| somlo | _florent_: Still not *the* answer, but for LiteSPI, the example should probably have `litespi,num-cs = <1>`, not 2, here: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/buildroot/board/litex_vexriscv/patches/linux/0007-drivers-spi-add-LiteSPI-driver.patch#L24 | 20:54 |
| tpb | Title: linux-on-litex-vexriscv/0007-drivers-spi-add-LiteSPI-driver.patch at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 20:54 |
| somlo | if this means how many actual `cs` pins there are in the `spisdcard` pads, it's 1 on every set of pads on all platforms in litex[-boards] I could find, not sure why they'd have used 2 for the example... | 20:55 |
| somlo | if that makes sense to you, I'll add that to my kernel patch set as part of the litespi driver upgrade | 20:56 |
| zyp | what's the general opinion on wishbone-tool vs litex_server.py? | 21:47 |
| zyp | I'm having some problems getting litescope to work via wishbone-tool - works fine via litex_server.py | 21:48 |
| _florent_ | somlo: yes cases where we use 2 or more cs pins are rare, it's only useful on boards where multiple chips are using the same SPI lines | 21:53 |
| _florent_ | somlo: i've not been able to test the SDCard in SPI mode with Linux-on-LiteX-Vexriscv, but will do some testing tomorrow | 21:54 |
| _florent_ | zyp: litex_server is probably slower and has less features than wishbone-tool, but that's what i'd recommend at first for LiteScope if you don't need specific features from wishbone tool. I've only used wishbone-tool for the specific cases that were not possible with litex_server (ex UART in Crossover mode over Etherbone) and it was working great, but i haven't tested personally LiteScope with it. | 21:59 |
| zyp | yeah, I tested the crossover mode earlier, and then I figured I'd keep using it, and found stuff weren't working properly | 22:03 |
| zyp | but I haven't looked too hard into how it's failing yet, so I don't have enough info to properly report it yet | 22:04 |
| zyp | I'm also looking forward until ethernet works more stable on the colorlight board, I guess it'll be a lot faster to dump the litescope buffer over etherbone rather than the uart bridge :) | 22:09 |
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