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| somlo | _florent_, sajattack[m]: how do you guys format your sdcard? I used parted on linux to create a 2G fat16, then `mkdosfs -F 16 /dev/sdb1` to create the filesystem, then I copied two files (top.bit and boot.bin) to it (64bit rocket only needs one file, the BBL, which contains dt, kernel, and everything). Here's what I get when I try to boot it: https://pastebin.com/qmWzFGDX | 00:21 |
|---|---|---|
| tpb | Title: litex> spisdcardboot SD Card via SPI Initialising Reading MBR Partition 1 Inf - Pastebin.com (at pastebin.com) | 00:21 |
| sajattack[m] | I used gparted | 00:23 |
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| rjeschmi | looking for some help with examples of dual LiteEthPHYRGMIIs (if it is even possible) | 00:26 |
| rjeschmi | I don't really need them to do anything right now, but litex seems to rename the conflicting clock domains automatically | 00:27 |
| rjeschmi | I worked around that, but it failed at the very end anyway (shared cell issue, or something I can probably reproduce it, but I'm not sure it was a sane thing to do anyway) | 00:27 |
| somlo | sajattack[m]: what size partition ? | 00:28 |
| sajattack[m] | 4G | 00:29 |
| somlo | wait, does fat16 support that? | 00:29 |
| sajattack[m] | Yeah | 00:29 |
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| somlo | sajattack[m]: turns out the FAT datastructures were using 'unsigned long' to mean 4 bytes, which is only true on 32-bit CPUs (should be 'unsigned int' for portability to 64bit Rocket) -- see https://github.com/enjoy-digital/litex/pull/433 | 01:57 |
| tpb | Title: Support SPI-mode SDCard booting on Litex+Rocket (64bit) configuration by gsomlo · Pull Request #433 · enjoy-digital/litex · GitHub (at github.com) | 01:57 |
| sajattack[m] | oh interestin | 01:59 |
| sajattack[m] | good ol' C variable width types | 01:59 |
| somlo | got it booting on 64-bit Rocket Chip enabled Litex -- \o/ :) | 01:59 |
| sajattack[m] | sweet | 02:00 |
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| rjeschmi | somlo: sounds cool | 02:53 |
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| _florent_ | somlo: great you got it working with Rocket and thanks for the PR, i'll test it with Vexriscv and merge if working. | 06:42 |
| _florent_ | rjeschmi: for the dual LiteEthPHYRGMII, can you create an issue on https://github.com/enjoy-digital/liteeth with your code and info to reproduce the issue? | 06:43 |
| tpb | Title: GitHub - enjoy-digital/liteeth: Small footprint and configurable Ethernet core (at github.com) | 06:43 |
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| rjeschmi | _florent_: sure I'll do that when I wake up. Thanks. I don't really know litex or migen well. | 11:50 |
| rjeschmi | The only code I found kind of interesting was a dual HDMI in hdmi2usb | 11:51 |
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| rjeschmi | _florent_: it seems like my problem is that they have a shared RESET pin, but are in two different clock domains | 12:54 |
| rjeschmi | ERROR: Cell 'eth0_rst_n$tr_io' cannot be bound to bel 'X0/Y47/PIOD' since it is already bound to cell 'eth1_rst_n$tr_io' | 12:55 |
| rjeschmi | I'll keep poking at it though | 12:55 |
| daveshah | Sounds like it is creating two resets with the same physical pin | 13:06 |
| rjeschmi | daveshah: yeah I think so https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/colorlight_5a_75b.py | 13:14 |
| tpb | Title: litex-boards/colorlight_5a_75b.py at master · litex-hub/litex-boards · GitHub (at github.com) | 13:14 |
| rjeschmi | looking at rst_n for the two eths | 13:14 |
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| rjeschmi | if there happens to be other examples out there of this it might help to me to learn a bit. | 13:15 |
| rjeschmi | I'm making some progress anyway | 13:15 |
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| rjeschmi | I commented out the shared pins just to see if I could get it to compile. It did. I am pushing the svf to see if it will function now :) | 13:55 |
| rjeschmi | These don't seem to be in an "eth" clock domain, so it must be something else related to how they are defined | 13:58 |
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| _florent_ | rjeschmi: using the 2 ethernet ports on the colorlight seems quite ambitious for now since it's already not passing timing with one :) | 17:38 |
| _florent_ | rjeschmi: but i could have a look to see if we can make it build | 17:38 |
| rjeschmi | Yeah fair enough :) | 17:38 |
| rjeschmi | I'm not really blocked. I'll just work on the one. I feel like maybe the reset mdio need to be handled differently | 17:40 |
| rjeschmi | I'll get a soft cpu working with the one ethernet mainly to get some sort of communications set up | 17:41 |
| _florent_ | have you been able to build the design by commenting the rst_n pin of the second phy? | 17:41 |
| rjeschmi | It is pretty limiting when UART isn't really possible | 17:41 |
| rjeschmi | Yeah, the build "worked" | 17:41 |
| rjeschmi | the first ethphy is pingable | 17:41 |
| rjeschmi | second is not | 17:42 |
| _florent_ | ok | 17:42 |
| rjeschmi | so I guess it must have built something, but I can't see what it did really | 17:42 |
| rjeschmi | I'm thinking getting softcpu with one ethernet to see some of the other bits | 17:42 |
| rjeschmi | thanks for the response however, it is a fun learning exercise :) | 17:43 |
| _florent_ | rjeschmi: in fact i'm not sure i got the second phy working on this board, even with a single phy in the design | 17:43 |
| _florent_ | (ie just by changing https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/colorlight_5a_75b.py#L77 to eth_phy=1) | 17:44 |
| tpb | Title: litex-boards/colorlight_5a_75b.py at master · litex-hub/litex-boards · GitHub (at github.com) | 17:44 |
| rjeschmi | I can test that | 17:44 |
| rjeschmi | I'll do that too just to check | 17:44 |
| _florent_ | but some work need to be done to improve timings: https://github.com/litex-hub/litex-boards/issues/40 | 17:44 |
| tpb | Title: Colorlight-5a-75b: Optimize IP/UDP/Etherbone timings, add SDRAM · Issue #40 · litex-hub/litex-boards · GitHub (at github.com) | 17:44 |
| _florent_ | so i'm not sure the issue was related to the timings or something else | 17:44 |
| rjeschmi | yeah I saw the timing discussion too | 17:45 |
| _florent_ | btw, this could be of interested for you: https://github.com/enjoy-digital/liteeth/pull/36 | 17:45 |
| tpb | Title: mac: add crossbar for sharing PHY between HW ethernet cores and Wishbone by piotr-binkowski · Pull Request #36 · enjoy-digital/liteeth · GitHub (at github.com) | 17:45 |
| _florent_ | it will probably change a little bit, but it allow sharing the PHY/MAC between the CPU and hardware | 17:46 |
| rjeschmi | yeah that looks promising | 17:47 |
| rjeschmi | I have an ethernet switch with port mirroring, so I can take a look at what is on those lines anyway | 17:48 |
| rjeschmi | I'll play around a bit and report back | 17:48 |
| _florent_ | ok thanks | 17:59 |
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| rjeschmi | _florent_: yeah, second phy doesn't seem to function, even alone. That is odd. I'll try to check the pins | 20:18 |
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