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| acathla | I have a new Versa Development Kit but with an ECP5 not the ECP5-5G configured by default everywhere in litex-boards, etc. | 15:42 |
|---|---|---|
| acathla | What's the best way to add support for that board? | 15:42 |
| acathla | http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/ECP5VersaDevelopmentKit.aspx | 15:43 |
| tpb | Title: ECP5 Versa Development Kit - Lattice Semiconductor (at www.latticesemi.com) | 15:43 |
| somlo | acathla: https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/versa_ecp5.py#L222 | 15:46 |
| tpb | Title: litex/versa_ecp5.py at master · enjoy-digital/litex · GitHub (at github.com) | 15:46 |
| somlo | also line 265 in the same file | 15:46 |
| somlo | I guess that stuff comes from https://github.com/enjoy-digital/litex/blob/master/litex/build/lattice/trellis.py | 15:47 |
| tpb | Title: litex/trellis.py at master · enjoy-digital/litex · GitHub (at github.com) | 15:47 |
| somlo | yours is probably this one: https://github.com/enjoy-digital/litex/blob/master/litex/build/lattice/trellis.py#L101 | 15:47 |
| tpb | Title: litex/trellis.py at master · enjoy-digital/litex · GitHub (at github.com) | 15:47 |
| somlo | daveshah would know more, though | 15:48 |
| acathla | Yes it works by changing a line | 15:48 |
| acathla | I was looking for a better way | 15:50 |
| somlo | maybe adding a parameter to versa_ecp5.py that optionally picks the non-5g architecture? | 15:51 |
| somlo | s/parameter/command-line option/ | 15:51 |
| _florent_ | acathla: you could do something like: https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/netv2.py#L190 or https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/ulx3s.py#L74 | 16:01 |
| tpb | Title: litex/netv2.py at master · enjoy-digital/litex · GitHub (at github.com) | 16:01 |
| somlo | _florent_: somewhere between 21d38701 and 4a15c3e2 I lost the ability to build LiteX + Rocket for (any) FPGAs (trellisboard and nexys4ddr hang after displaying "__ _" (the top of 'L' and 'i' of the bootsplash logo) | 16:06 |
| somlo | still works in the simulator, so that's not useful to troubleshoot :) | 16:06 |
| somlo | first problem is we need an "from litedram.frontend.axi import LiteDRAMAXI2Native" in soc/integration/soc.py for the direct point-to-point rocket <-> litedram path | 16:08 |
| somlo | but that's just to compile the bitstream, which then hangs | 16:08 |
| somlo | tried to bisect, but I keep landing on commits that won't build for other reasons, so for now I'm stuck... | 16:08 |
| acathla | _florent_, perfect. Should I create a pull-request? | 16:35 |
| daveshah | somlo: may or may not be relevant, I had that problem when doing some VexRiscv debugging a while ago and it was interrupt related in the end | 16:37 |
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| somlo | daveshah: interrupts is what I suspect as well -- I almost wish the simulator had been broken too, that way debugging would have been much faster :) | 16:47 |
| somlo | probably going to start removing anything with an IRQ that isn't also present on the simulator (probably LiteETH), and see if that influences the outcome in any way... | 16:48 |
| somlo | daveshah: also, with the new soc.py, rocket on ecp5_versa is back to 101% slice utilization... So I'm only able to try things on the trellisboard and the nexys4ddr (with vivado) | 16:50 |
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| _florent_ | somlo: sorry for that, i can help finding what is going on. For the resource usage, the only change i can think of is the L2 Cache when i change the default behavior to use FullMemoryWE by default, you can try to set to false here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L904 | 17:10 |
| tpb | Title: litex/soc.py at master · enjoy-digital/litex · GitHub (at github.com) | 17:10 |
| _florent_ | somlo: for the functional regression, in the log, can you check that all Bus Regions are what you expect? (origin, size, mode, cached?) | 17:11 |
| _florent_ | acathla: yes sure a PR is welcome | 17:11 |
| _florent_ | somlo: while doing this, i indeed tested regression with Rocket only in simulation. Last time i had a similar issue, it was caused by a CSR mapping issue. | 17:13 |
| somlo | _florent_: thanks for the tips, I'll keep digging. Do you want the soc/integration/soc.py "from litedram.frontend.axi import LiteDRAMAXI2Native" as a PR, or would you rather just add it in directly? | 17:16 |
| _florent_ | somlo: that's fine, i'll add it, thanks | 17:16 |
| somlo | (I'm using direct point-to-point AXI between Rocket and LiteDRAM, so I need that extra import) | 17:16 |
| acathla | I've got an error when programming the Versa board :Error: tdo check error at line 11 | 17:17 |
| acathla | Error: READ = 0x2224086 | 17:17 |
| acathla | Error: WANT = 0x41112043 | 17:17 |
| acathla | The example of prjtrellis still works fine with this error (Hello, World, etc on the LED), but that's all. OpenOCD too old? | 17:18 |
| _florent_ | acathla: strange, seems shifted by 1 bit | 17:19 |
| _florent_ | somlo: i pushed the fix | 17:19 |
| _florent_ | somlo: are you running the simulation with direct point-to-point? | 17:19 |
| _florent_ | somlo: btw, it's now possible to simulate with any type of memory (--sdram-module) and any data width (--sdram-data-width), so even if the simulation does not default to point-to-point, you should be able to test it | 17:21 |
| somlo | _florent_: I didn't simulate with any memory, so no to your first question | 17:23 |
| somlo | I did try the wishbone converter option (different litedram port width than rocket's axi port), which forces the wishbone conversion, got the same results | 17:24 |
| somlo | _florent_: like daveshah mentioned, the fact that I get three or four putchars before things hang *feels* like an IRQ problem | 17:24 |
| somlo | so I'm going to try turning off LiteETH when building bitstream next, to see if that makes a difference | 17:25 |
| somlo | it's the only thing with an IRQ that's not in the default simulator config that I can think of :) | 17:25 |
| _florent_ | somlo: i already add a similar issue with a cached/uncached CSR mapping issue (IIRC CSR was mapped to a cached region) | 17:26 |
| somlo | ok, so I need to make sure that in my case no CSRs are mapped above 0x80000000 (which is Rocket's cached region, routed through its mem_axi port) | 17:27 |
| _florent_ | somlo: we have the current mapping in Rocket: | 17:28 |
| _florent_ | https://www.irccloud.com/pastebin/QIsOp3Kf/ | 17:28 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 17:28 |
| _florent_ | for others CPU, we are putting rom and sram in a cached region | 17:28 |
| somlo | right, rocket overrides the mem_map property, and everything (rom, sram, csr) is accessed uncached via the mmio-axi port that's converted to wishbone and ends up as the wishbone bus master | 17:29 |
| somlo | 0x80000000 and above goes through rocket's internal L1 cache, and out via the mem-axi port | 17:30 |
| somlo | and looking through csr.csv for my latest nexys4ddr build, all CSRs are below 0x80000000, where they *shold* be -- so accessing CSRs through the cache doesn't seem to be my issue | 17:32 |
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| somlo | _florent_, daveshah: so I tried "litex/litex/tools/litex_sim.py --csr-data-width 32 --with-ethernet --cpu-type rocket" from a freshly cloned repo (still bisecting inside my main one :) ) | 19:15 |
| somlo | and it still works | 19:15 |
| somlo | was hoping the ethernet thing will trigger the bug I saw on the fpga, but no :) | 19:16 |
| _florent_ | somlo: FYI i tried a build on Arty and reproduced your issue | 19:16 |
| somlo | _florent_: thanks for the confirmation, and sorry to be the bearer of bad news :) | 19:17 |
| somlo | I had to skip a couple of commits during bisect, still hoping to narrow down the list of things to look at for clues (not sure that'll end up being useful, but since I started it I'll take it as far as I can)... | 19:18 |
| _florent_ | that's better to know it now than later :), i could do more tests tomorrow, if you bisect it more closely, please post here the commits, i'll try to understand | 19:19 |
| somlo | will do, and thanks again! | 19:20 |
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| _florent_ | somlo: i found a regression on CSR alignment with Rocket (it was set to 32 instead of 64), i'm building a SoC on Arty with the fix | 20:15 |
| somlo | _florent_: for better or worse, bisect blames commit 29bbe4c0 :) | 20:15 |
| somlo | not sure if that's consistent with what you found, and I just got that information 5 seconds ago, so I haven't looked inside yet :) | 20:16 |
| somlo | "add add_csr_bridge method" ring a bell ? | 20:16 |
| _florent_ | at least it's related to CSR :) | 20:17 |
| somlo | that's encouraging, yeah | 20:18 |
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| _florent_ | https://github.com/enjoy-digital/litex/commit/5b34f4cd34b6f827f7d0c2d3c97560b99873d8b2 works on Arty :) | 20:28 |
| tpb | Title: soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on R… · enjoy-digital/litex@5b34f4c · GitHub (at github.com) | 20:28 |
| somlo | building on trellisboard now... | 20:30 |
| somlo | _florent_: while I'm waiting for the build, I dug around, and it was actually commit 84b5df78 that removed the line "csr_alignment = self.cpu.data_width" from soc_core.py | 20:41 |
| somlo | which is where we used to adjust alignment, specifically for rocket at that time | 20:42 |
| somlo | so I guess if I have to "git bisect skip", I may end up randomly blaming the wrong commit for whatever upsets me at that moment :) | 20:43 |
| somlo | the more interesting question to me is, why was this working in simulation ? :) | 20:49 |
| somlo | _florent_: \o/ | 21:08 |
| somlo | it now hangs during Linux boot when attempting to initialize the LiteETH driver, but that probably means I have to redo the driver initialization to account for whatever changes occurred in LiteETH over the last few days | 21:09 |
| somlo | either way, thanks for catching the alignment thing! | 21:09 |
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