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| levi | Argh. I've got my LiteEth ethernet to the point where mdio works, gigabit link is established, but the other end just racks up its fcs error counter when I try to send anything. I assume something is wrong with the RGMII interface somehow, but it's difficult to see what it is. | 05:04 |
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| davidc__ | levi: can you put your PHY in a loopback mode? | 05:36 |
| levi | Hmm, yeah; looks like there's a bit for that in the MII Control Register. | 05:51 |
| levi | I've done that and it doesn't seem to have registered any particular errors. I've currently only got the bios loaded, so I can read and write mdio registers and attempt to netboot. | 06:01 |
| levi | I need a NIC that'll let me see bad frames to see how these are getting mangled. | 06:13 |
| levi | Woo, one of them *does* have such a setting. And the packets don't seem too mangled after all. | 06:46 |
| levi | Not so much mangled as truncated; and receive seems to work, at least enough for the ARP response to be understood. | 06:51 |
| levi | Maybe this is actually a software issue? | 06:53 |
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| sajattack[m] | oh that's what [m] means in a username, matrix bridge, TIL | 07:10 |
| sajattack | /exit | 07:11 |
| sajattack | oops | 07:11 |
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| sajattack[m] | I love irssi and all but I think I'll hang out over here instead, sorry for offtopic | 07:12 |
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| _florent_ | levi: can you tell us which FPGA you are using? | 08:17 |
| _florent_ | levi: a few things you can to do help debugging: set this to False: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/mac/__init__.py#L11 | 08:19 |
| tpb | Title: liteeth/__init__.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 08:19 |
| _florent_ | this will disable hardware PREAMBLE/CRC and will make the software manage it. (so if you have a CRC error on the RX, the software will still see it) | 08:19 |
| _florent_ | and activate the debug traces in the software: | 08:20 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/libnet/microudp.c#L21-L22 | 08:20 |
| tpb | Title: litex/microudp.c at master · enjoy-digital/litex · GitHub (at github.com) | 08:20 |
| _florent_ | now be sure to be able to capture malformed frame on your computer (ie avoid any switch, router, etc...) | 08:21 |
| _florent_ | and you should now be able to see packet on the two side: the BIOS will show the TX/RX packets and you should be able to compare with what you have one your computer | 08:22 |
| levi | It's a Spartan 6, XC6SLX45, hooked up to a Broadcom 5482 dual-PHY, although I've only got the first one hooked hooked up to LiteEth now. | 08:29 |
| levi | I did figure out how to get debug tracing turned on in microudp, and I've got my NIC on my Linux+wireshark setup configured to give me malformed packets. | 08:30 |
| levi | So, it appears that I'm receiving just fine via LiteEth, so the hardware preamble/CRC works on that path. And the preamble seems to work on the tx side, and probably the crc would too but for some reason all the received frames in Wireshark stop (i.e. turn to all 00s) after 42 bytes. | 08:32 |
| levi | That's enough for the useful fields of the initial ARP to get received, so a response is sent and the netboot code sends the first UDP packet; it's truncated right at 42 bytes though which is just to the end of the UDP header. The debug printout on the console shows that the tx buffer was fully filled out, though. | 08:34 |
| _florent_ | What frequency are you using on the CPU? i remember @daveshah and @gsomlo has issue with low frequencies (50/60MHz) and 1Gbps Ethernet | 08:39 |
| daveshah | Yes, I found it was 55MHz minimum for working 1Gbps TFTP | 08:40 |
| levi | I sent the board some 512 byte pings while it was attempting netboot to see if it would rx the entire payload, and it does print out the whole thing on the console. | 08:40 |
| levi | It's just tx that's not working. | 08:41 |
| levi | It's currently at 50MHz; I'll have to look at the timing report to see if I can crank it faster. | 08:41 |
| daveshah | Yes, 50MHz doesn't work afaik | 08:42 |
| daveshah | I think it was the Tx that was broken for me too | 08:42 |
| levi | Odd. | 08:42 |
| daveshah | I think it is some kind of underflow in liteeth | 08:43 |
| daveshah | But I never spent much time looking in detail | 08:43 |
| _florent_ | levi: can you try increasing the depth of the TX fifo here: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/mac/core.py#L104 | 08:44 |
| tpb | Title: liteeth/core.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 08:44 |
| _florent_ | try something like 256 or 512 | 08:44 |
| _florent_ | i just created: https://github.com/enjoy-digital/liteeth/issues/30 | 08:47 |
| tpb | Title: Netboot issues with 1Gbps and low CPU frequency (<55MHz) · Issue #30 · enjoy-digital/liteeth · GitHub (at github.com) | 08:47 |
| levi | The timing report suggests I could maybe do 100MHz, but I'll try the tx FIFO first. I really appreciate the help! | 08:47 |
| levi | This board also doesn't bother with pin-strap configuring of the Phy, so it took me a while to figure out how to get it to decide it could do better than half-duplex 10BaseT. | 08:52 |
| levi | 256 didn't seem to help; trying with a faster sysclk this time. | 08:58 |
| levi | Well, ethernet tx works now! Unfortunately something broke the SDRAM with the clock increase. | 09:08 |
| _florent_ | OK thanks for the feedback, what frequency are you using now? | 09:12 |
| _florent_ | i'm going to do some tests to see if i understand | 09:13 |
| levi | 100MHz. I think I just need to adjust the SDRAM clocks to maintain the same relationship as they had at 50MHz? | 09:15 |
| _florent_ | yes but DDR is not easy to get working correctly on Spartan6 | 09:16 |
| _florent_ | (mainly due to the PHY in LiteDRAM that should be refreshed) | 09:16 |
| _florent_ | i'm going to do some tests with the Versa ECP5 / 1Gbps Ethernet and 50MHz clock to see if i reproduce and then investigate | 09:17 |
| Xiretza | hey, what exactly does the standalone liteeth core do? README says the frontend is etherbone (which is wishbone over UDP as far as I can tell), but then `gen.py --core` takes either "wishbone" or "udp". My goal is to somehow end up with a memory-mapped peripheral in my traditional SoC I can use for arbitrary ethernet, can liteeth help me with that? | 09:18 |
| levi | "wishbone" is what you want for a CPU-managed core, assuming the CPU has a wishbone interface as well. | 09:20 |
| Xiretza | I can make that happen, how does the wishbone interface work then? is it basically just two fifos for RX and TX? any specs? | 09:22 |
| levi | It's a fully-documented spec, yeah. | 09:23 |
| levi | _florent_: I doubled the clocks on the RAM and it came right back, so I appear to be in business now! Thanks for your help! | 09:25 |
| _florent_ | Xiretza: sorry, the Etherbone frontend is not yet integrated in the generator, for now you can the generator can create a MAC+PHY (to be used with a CPU) or hardware IP/UDP stack and expose UDP ports | 09:26 |
| _florent_ | Etherbone can be already be used when integrated with LiteX | 09:27 |
| Xiretza | levi: do you mean wishbone itself or liteeth's interface? I have the wishbone spec, I'm just not sure how liteeth's logical interface works. | 09:28 |
| _florent_ | You can then create a Wishbone Master on the SoC bus and do the access with your computer | 09:28 |
| _florent_ | can you explain a bit more your usecase? "My goal is to somehow end up with a memory-mapped peripheral in my traditional SoC I can use for arbitrary ethernet, can liteeth help me with that?" | 09:29 |
| _florent_ | levi: great if you got it working (i will still investigate the issue with the slow CPU clock) | 09:31 |
| levi | Well it passes the SDRAM bootup memtest; I'm not sure how thorough that is. And ethernet tx/rx seem to be working; I haven't got the tftp boot server up yet though. That'll be a task for tomorrow! | 09:34 |
| Xiretza | _florent_: I'm building a RISC-V core and peripherals in VHDL as part of my end-of-school project, and since the Arty A7 board I'm using also has an ethernet PHY, I'd love to integrate it as well. Having to do all the MII interfacing myself would be annoying, so something that does that (but not necessarily a full UDP stack) would be nice to have. | 09:36 |
| _florent_ | levi: if it passes memtest, it should be fine | 09:38 |
| _florent_ | Xiretza: ok, then you probably want to use the generator to generate a core that integrate the PHY + MAC + SRAM + Wishbone interfaces | 09:39 |
| _florent_ | you will then just have to connect it as a Wishbone Slave of your system and access it the same way it's done in the LiteX BIOS | 09:40 |
| Xiretza | _florent_: yeah, that seems like the best course of action - my question now is about the wishbone interface `--core wishbone` exposes though, is the LiteX BIOS the reference implementation? | 09:42 |
| levi | OK, I lied; I got the tftp server running and booted the firmware! Now I'm off to sleep though. Thanks again. :) | 09:50 |
| levi | Xiretza: https://opencores.org/howto/wishbone | 10:07 |
| _florent_ | Xiretza: yes, you can use the software from the BIOS as a reference to use the generated core | 10:25 |
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| Xiretza | levi: maybe I'm misunderstanding, but the wishbone specification doesn't tell me how to interface with an ethernet MAC, right? that's what a "wishbone datasheet" (WB spec section 2.1) is for, which I can't find for liteeth. | 10:28 |
| _florent_ | Xiretza: indeed, there are no current documentation for that, except the current software: | 10:30 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/libnet/microudp.c | 10:30 |
| tpb | Title: litex/microudp.c at master · enjoy-digital/litex · GitHub (at github.com) | 10:30 |
| _florent_ | you can also find the linux driver here: https://github.com/litex-hub/linux-on-litex-vexriscv/tree/master/buildroot/board/litex_vexriscv/patches/linux | 10:31 |
| tpb | Title: linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/patches/linux at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 10:31 |
| Xiretza | alright, that settles that, I'll have a look at the sources then. thank you all for the help! | 10:31 |
| _florent_ | daveshah, somlo, levi: i just fixed the ethernet issue, it was just related to the way the accesses were done on the TX SRAM: https://github.com/enjoy-digital/liteeth/issues/30#issuecomment-583335583 i tested it at 30MHz successfully on the Versa ECP5 | 10:49 |
| tpb | Title: Netboot issues with 1Gbps and low CPU frequency (<55MHz) · Issue #30 · enjoy-digital/liteeth · GitHub (at github.com) | 10:49 |
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| *** _florent_ changes topic to "LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex" | 11:15 | |
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| somlo | _florent_: got rocket/litex going at 40MHz on the trellisboard, with ethernet :) | 17:59 |
| somlo | so I can confirm it works | 17:59 |
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| somlo | maybe I should re-try nfs-root (while I keep poking at litesdcard in the background) :) | 18:00 |
| _florent_ | somlo: great, thanks for the feedback, i hope it will be useful for your tests | 18:00 |
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| sajattack[m] | _florent_: around? | 19:43 |
| sajattack[m] | I'm finally getting around to trying to set up vga | 19:44 |
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| sajattack[m] | linux_on_litex is trying to do hdmi still though, it grabbed hdmi_out rather than vga_out from platform, and it's erroring on hdmi stuffs in litevideo/output/driver.py | 19:45 |
| sajattack[m] | oh I see | 19:45 |
| sajattack[m] | the vga check is looking for hsync_n, but I have hsync | 19:46 |
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| sajattack[m] | is the bios meant to output vga? | 20:13 |
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| sajattack[m] | linux is hanging on simple-framebuffer initialization | 20:37 |
| sajattack[m] | possibly I did the clock wrong | 20:37 |
| sajattack[m] | is the clock domain supposed to be called cd_pix or just pix? | 20:41 |
| _florent_ | sajattack[m]: the bios is not outputing anything no | 20:42 |
| _florent_ | you need to create a clock domain similar to self.clock_domains.cd_pix = ClockDomain() | 20:43 |
| sajattack[m] | ok, linux isn't outputting either | 20:43 |
| sajattack[m] | ok that's what Ihad | 20:43 |
| _florent_ | and do self.comb += self.cd_pix.clk.eq(your_generated_clk) | 20:43 |
| sajattack[m] | * ok that's what I had | 20:43 |
| sajattack[m] | yup yup | 20:43 |
| sajattack[m] | this made me think maybe it was just called pix https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py#L152 | 20:44 |
| tpb | Title: linux-on-litex-vexriscv/soc_linux.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 20:44 |
| _florent_ | maybe connect do some checks on this clock: make a counter with it and connect if to a led | 20:44 |
| sajattack[m] | yeah I'm also not sure if the pll params I chose are possible | 20:45 |
| sajattack[m] | maybe I'll try to run at 75mhz instead of 74.125 | 20:45 |
| sajattack[m] | should be close enough | 20:46 |
| sajattack[m] | (720p) | 20:46 |
| sajattack[m] | I've run 480p off a 24mhz clock before | 20:48 |
| sajattack[m] | totally unrelated project tho | 20:48 |
| sajattack[m] | if the timing analyzer says "found 1 clocks", does that mean the other 2 got trimmed out? | 20:54 |
| sajattack[m] | I guess you're probably not intimately familiar with altera | 20:54 |
| sajattack[m] | * I guess you're probably not intimately familiar with altera tools | 20:54 |
| sajattack[m] | * I guess you're probably not intimately familiar with altera tools | 20:54 |
| sajattack[m] | oh | 21:02 |
| sajattack[m] | I forgot --with-sdram | 21:02 |
| sajattack[m] | fml | 21:02 |
| sajattack[m] | actually it shouldn't matter because linux-on-litex does that automatically | 21:02 |
| sajattack[m] | _florent_: can you give this a quick spot check? https://termbin.com/zu1u7 | 21:14 |
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| scanakci | I guess I figured out why LiteDRAM was not working with BlackParrot on FPGA. | 22:43 |
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| scanakci | https://usercontent.irccloud-cdn.com/file/j9YUcMVd/BlackParrot_memtest | 22:44 |
| scanakci | finally, passing the memtests | 22:44 |
| scanakci | Next step is to use LiteETH. | 22:44 |
| scanakci | _florent_: could you have a chance to look at my PR? I guess travis fails since I need to use a larger ROM than default. Let me know if there are other issues :) | 22:45 |
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