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| xobs | Is there a recommended way to get litex working on a system without much room for a rom? | 02:42 |
|---|---|---|
| xobs | On Fomu I hacked it by coming up with my own "bios" target and redirecting it, but that was painful to set up. | 02:43 |
| xobs | Esden is porting litex to the icebreaker, and he'll run into the limitation now | 02:43 |
| xobs | I managed to get the bios to work on Fomu by stripping out almost everything but I gather that's not the recommended way of doing it. | 02:44 |
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| esden | o/ :) | 04:16 |
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| xobs | So the thing I did for esden to get it to work was https://github.com/xobs/litex-boards/blob/icebreaker/litex_boards/partner/targets/icebreaker.py#L202 which sets the `rom` memory region to point to just after the bitstream. | 07:31 |
| tpb | Title: litex-boards/icebreaker.py at icebreaker · xobs/litex-boards · GitHub (at github.com) | 07:31 |
| xobs | I had to hack it that way because litex has a check to make sure it's along some boundary, which the address `0x2001a000` doesn't satisfy. Is there a better way to do that? | 07:31 |
| _florent_ | Hi xobs, esden, if you are able to use the SPI Flash to store the BIOS and execute it from there, then that's what i would recommend yes | 07:38 |
| xobs | Okay, he's reported that it works, so that's what I'll stick with. | 07:39 |
| xobs | The problem comes from the fact that `spiflash` is already at that offset, so I use that trick to avoid that conflict error. | 07:39 |
| xobs | Also, it's at `0x1a000` from the start, which isn't block-aligned. | 07:40 |
| _florent_ | xobs: ok, i'm going to compare what you did with what we use on others designs for that | 07:43 |
| xobs | It's a common enough pattern, but this is the first time I've decided to try and work with the bios build system rather than scrapping it. Also he doesn't really need a bootloader or a bios in this case. | 07:44 |
| _florent_ | xobs: here is how it's done in litex-buildenv: https://github.com/timvideos/litex-buildenv/blob/master/targets/mimasv2/base.py#L213-L229 | 07:51 |
| tpb | Title: litex-buildenv/base.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 07:51 |
| _florent_ | xobs: to define a memory region that will only be used by the linker (and that overlap with another already defined memory region), you can add the "+linker" to the type. | 07:52 |
| _florent_ | xobs: but i agree this should be simplified | 07:53 |
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| mithro | _florent_ / xobs: That is something I would like to be solved too | 08:33 |
| mithro | _florent_ / xobs: I really think we should also invest in solving the spiflash issue and finishing of the spi flash module system I was working on | 08:33 |
| xobs | mithro: I think speeding up SPI flash would be more helpful. esden was having trouble getting anything working because it would time out after 500 ms. | 08:34 |
| mithro | https://docs.google.com/document/d/1JZ7pU7roOaJwsv_LlXDKpWrLMSp254-tuof5KIFcC-I/edit# | 08:34 |
| tpb | Title: LiteX SPI Flash Improvements - Google Docs (at docs.google.com) | 08:34 |
| mithro | xobs: What was timing out? | 08:34 |
| xobs | Ended up needing to switch to the `lite` core to get the BIOS to finish. | 08:34 |
| xobs | mithro: wishbone. `wishbone-tool` has a timeout of one second, so if the bridge doesn't respond within that time, it assumes the bus has locked up. | 08:35 |
| mithro | xobs: https://github.com/mithro/litex/tree/d7184b97494012a8c21ee93df231b758a61e9dec/litex/soc/cores/spi | 08:35 |
| tpb | Title: litex/litex/soc/cores/spi at d7184b97494012a8c21ee93df231b758a61e9dec · mithro/litex · GitHub (at github.com) | 08:35 |
| mithro | xobs: I agree that speeding up the core would be good too | 08:37 |
| xobs | It would help both fomu and icebreaker. | 08:37 |
| mithro | xobs: Putting the spiflash in a different clock domain (which is much faster) would be a big improvement | 08:39 |
| mithro | xobs: Would it help for betrusted at all? | 08:39 |
| xobs | mithro: It might! One thing I've found is that using 32-bit CSRs gives us much better timing. I see it meeting up to 60 MHz for the 48 MHz domain, versus the 50 MHz we were seeing before. | 08:40 |
| mithro | xobs: Interesting... | 08:40 |
| mithro | _florent_: I was looking at your changes and I don't feel like all the csr/bus width checking stuff belongs in the area you put it | 08:42 |
| _florent_ | mithro: indeed, i was also thinking the same after doing it, but this was just a sketch to show you that we have the same general ideas, i just need to spend more time working on that to refine things | 09:13 |
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| feig | Has anyone built litedram on VC707? I noticed that the V7DDRPHY is there, and the SO-DIMM module is the same as the one used in KC705. So I basically copied the setting(clock freq, termination resistance) for KC705. But the memory initialization failed. | 21:17 |
| daveshah | I think an issue like this was discussed recently | 21:17 |
| daveshah | https://github.com/enjoy-digital/litex/issues/361 | 21:18 |
| tpb | Title: KC705 DDR3 calibration regression · Issue #361 · enjoy-digital/litex · GitHub (at github.com) | 21:18 |
| feig | Thank you very much! that helps a lot | 21:20 |
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