| *** tpb has joined #litex | 00:00 | |
| *** rohitksingh has joined #litex | 01:02 | |
| *** rohitksingh has quit IRC | 01:10 | |
| *** rohitksingh has joined #litex | 01:15 | |
| *** xobs has quit IRC | 01:40 | |
| *** rohitksingh has quit IRC | 03:10 | |
| *** xobs has joined #litex | 03:38 | |
| xobs | Yeah, I do have /dev/ptmx in WSL, but I'm not sure if that's available in Windows-land. | 03:38 |
|---|---|---|
| *** CarlFK has joined #litex | 04:38 | |
| *** futarisIRCcloud has quit IRC | 05:55 | |
| *** CarlFK has quit IRC | 05:57 | |
| *** CarlFK has joined #litex | 06:01 | |
| *** futarisIRCcloud has joined #litex | 06:22 | |
| keesj | from the link I send yesterday it was introduced in windows 10 insiders preview SDK (I normally don't run windows but go quite exited by wsl) | 06:48 |
| xobs | Hey, is anyone running Linux on RISCV? | 06:54 |
| xobs | I'm curious what happens when you attempt to write to SATP from User mode. I'm using Renode, and the write succeeds and disables the MMU, which seems wrong, but I haven't yet found out what it's supposed to do. | 06:55 |
| xobs | Ah, it looks like it should raise illegalAccess: https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/plugin/CsrPlugin.scala#L1040 | 07:08 |
| tpb | Title: VexRiscv/CsrPlugin.scala at master · SpinalHDL/VexRiscv · GitHub (at github.com) | 07:08 |
| xobs | Even though it doesn't in Renode. | 07:40 |
| xobs | So does anyone have a Linux handy that's running on Vex? I've got a simple program that should crash. Under Renode it takes down the whole system, but I suspect that's a bug. | 07:40 |
| CarlFK | xobs: what's vex? | 08:01 |
| xobs | CarlFK: vexriscv | 08:01 |
| xobs | I'm trying to get verilator to work now so I can test it out. Seems like the perfect usecase. | 08:02 |
| CarlFK | ah no. | 08:02 |
| _florent_ | xobs: not sure if that can be useful, but in linux-on-litex-vexriscv, we have a simulation (using verilator) that can boot Linux with VexRiscv: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/sim.py | 10:39 |
| tpb | Title: linux-on-litex-vexriscv/sim.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 10:39 |
| _florent_ | https://github.com/litex-hub/linux-on-litex-vexriscv#running-the-litex-simulation | 10:40 |
| tpb | Title: GitHub - litex-hub/linux-on-litex-vexriscv: Linux on LiteX-VexRiscv (at github.com) | 10:40 |
| *** mithro has quit IRC | 10:56 | |
| *** mithro has joined #litex | 10:57 | |
| xobs | _florent_: thanks, that might help! I'm working to get something working in Verilator, but having Linux would help too. | 11:01 |
| *** rohitksingh has joined #litex | 13:45 | |
| *** guan has quit IRC | 14:53 | |
| *** guan has joined #litex | 14:53 | |
| xobs | _florent_: huh. That seems like unintended behavior. I ran that program in that simulator, and it quit verilator. | 15:08 |
| xobs | Ah, no, that's probably expected when it gets an illegal instruction. | 15:20 |
| _florent_ | xobs: yes, the CPU is probably writing the finish CSR on illegal instruction to stop the simulation | 15:25 |
| xobs | Right. Whereas with Renode, it actually gets stuck in user mode and the PC jumps to an invalid offset. Also, Renode will happily read satp all day. Currently starting verilator to see what happens if I try the same program there. I suspect it'll crash, too. | 15:38 |
| sorear | xobs: it should raise illegal instruction, not an access/page fault | 15:39 |
| sorear | basically everything in riscv is an illegal instruction unless there’s more specific handling | 15:40 |
| xobs | sorear: yeah, that's what I see under Verilator, but not under Renode: `CPU Exception: Illegal instruction 0x18002573 at 0x2050020c` | 16:26 |
| sorear | renode seems buggy with exceptions | 16:28 |
| *** rohitksingh has quit IRC | 16:40 | |
| *** rohitksingh has joined #litex | 17:09 | |
| *** rohitksingh has quit IRC | 17:33 | |
| *** rohitksingh has joined #litex | 17:57 | |
| *** rohitksingh has quit IRC | 18:07 | |
| *** rohitksingh has joined #litex | 19:43 | |
| *** rohitksingh has quit IRC | 19:49 | |
| *** rohitksingh has joined #litex | 20:42 | |
| *** rohitksingh has quit IRC | 21:39 | |
| *** rohitksingh has joined #litex | 23:01 | |
| *** CarlFK has quit IRC | 23:17 | |
| *** CarlFK has joined #litex | 23:37 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!