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| scanakci | is it possible not to include LiteX L2 Cache for the FPGA implementation? It is adding more complexity when I am debugging dram tests. I would like to have BP->LiteDRAM->DRAM for now. | 22:11 |
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| somlo | scanakci: it depends on the actual development board you're using. The LiteDRAM port width may be wider than 64bit (it's 128 on the ecp5 versa, could be 256 on other boards) | 23:17 |
| somlo | add a print statement here to find out about yours: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_sdram.py#L62 | 23:18 |
| tpb | Title: litex/soc_sdram.py at master · enjoy-digital/litex · GitHub (at github.com) | 23:18 |
| somlo | then, if you're lucky and it's 64 bits, you can s/self.l2_cache.slave/wb_sdram/ here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_sdram.py#L118 | 23:20 |
| tpb | Title: litex/soc_sdram.py at master · enjoy-digital/litex · GitHub (at github.com) | 23:20 |
| somlo | and comment out a bunch of stuff about setting up the l2 cache above that line | 23:21 |
| somlo | if you're not lucky, the l2 cache actually serves as a data width adapter between your LiteDRAM and your CPU | 23:21 |
| somlo | and so you're stuck with it :) | 23:21 |
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