| *** tpb has joined #litex | 00:00 | |
| *** CarlFK has quit IRC | 00:04 | |
| *** rohitksingh has joined #litex | 05:43 | |
| *** _whitelogger has quit IRC | 07:19 | |
| *** _whitelogger has joined #litex | 07:22 | |
| *** CarlFK has joined #litex | 08:50 | |
| *** _franck_ has quit IRC | 08:59 | |
| *** CarlFK has quit IRC | 09:49 | |
| *** _franck_ has joined #litex | 12:05 | |
| keesj | https://github.com/T-head-Semi/wujian100_open | 20:44 |
|---|---|---|
| tpb | Title: GitHub - T-head-Semi/wujian100_open: IC design and development should be faster，simpler and more reliable (at github.com) | 20:44 |
| somlo | https://github.com/T-head-Semi/wujian100_open#get-ready-for-fpga-bit-generation "1. make sure you have the synplify and license" | 23:28 |
| tpb | Title: GitHub - T-head-Semi/wujian100_open: IC design and development should be faster，simpler and more reliable (at github.com) | 23:28 |
| Finde | lol | 23:41 |
| Finde | been wondering about designware-compatible cleanroom implementations actually | 23:42 |
| Finde | it turns out that AnyCore relies on some designware components and I'd love to see it not have to | 23:43 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!