Wednesday, 2020-01-15

*** tpb has joined #litex00:00
*** CarlFK has quit IRC01:03
xobs_florent_: thanks, the new UART changes work well!  Tunneling via wishbone works, so now `wishbone-tool` can act as a terminal emulator via any of the bridges.02:19
xobsIt's also growing basic Etherbone support now.  So we can have terminal-over-Ethernet.02:20
*** CarlFK has joined #litex02:34
*** _whitelogger has quit IRC04:07
*** _whitelogger has joined #litex04:10
_florent_xobs: thanks, that will be very useful! I was always switching between the Wishbone Bridge and the CPU UART manually or using 2 UARTs to have both together07:08
xobsI also added the ability to run multiple servers at once, so terminal and gdb will both work. Though now I need to add the ability to run gdb on a different port.07:09
_florent_xobs: great. Do you have a board to test the terminal-over-Ethernet? I'm happy to do some testing if needed07:12
xobsmithro was working to get that built. There were Reasons that it doesn't work. Could you please help him get an image working?07:13
mithroI'm looking at it now07:14
_florent_mithro: which board are you using?07:14
mithro_florent_: I'm stuck at getting the wishbone bridge over ethernet working07:14
mithro_florent_: Arty07:14
_florent_mithro: are you able to ping the board?07:15
futarisIRCcloudThis stuff sounds great.07:17
mithro_florent_: Let me push what I have so far07:19
_florent_mithro: ok07:19
mithro_florent_: Also, would like your thoughts on https://github.com/enjoy-digital/litex/issues/34507:19
tpbTitle: Support register_mem autoselecting appropriate memory location · Issue #345 · enjoy-digital/litex · GitHub (at github.com)07:19
mithro_florent_: https://github.com/mithro/litex-buildenv/blob/etherbone/targets/arty/etherbone.py07:20
tpbTitle: litex-buildenv/etherbone.py at etherbone · mithro/litex-buildenv · GitHub (at github.com)07:20
mithro_florent_: It took me a while to realize that I have actually mostly done etherbone through libuip rather than with hardware07:21
_florent_xobs, mithro: it should be possible to easily test Etherbone with litex_sim: https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py07:23
mithro_florent_: I did get the ice40hx-evn board actually booting again07:23
tpbTitle: litex/litex_sim.py at master · enjoy-digital/litex · GitHub (at github.com)07:23
_florent_just remove the serial here: https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py#L116-L12007:23
tpbTitle: litex/litex_sim.py at master · enjoy-digital/litex · GitHub (at github.com)07:23
mithro_florent_: That is a probably a good idea for xobs to test with :-)07:23
_florent_set with_uart=True here and set uart_name="crossover"07:24
mithro_florent_: At the moment I'm trying to get that `arty/etherbone.py`to respond to pings on hardware07:25
_florent_https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py#L11107:25
tpbTitle: litex/litex_sim.py at master · enjoy-digital/litex · GitHub (at github.com)07:25
_florent_and then just run: litex_sim --with-etherbone07:25
_florent_then try to ping 192.168.1.5007:26
_florent_if its responding, the Etherbone bridge is responding and you can use it07:26
_florent_Etherbone bridge is responding/Etherbone bridge is active07:26
_florent_mithro: being able to use add_mem_region without the origin seems a good idea yes. When doing it we should just make sure to avoid breaking the old API and still allow using a fixed memory map07:29
mithro_florent_: I believe my python code does that07:30
mithro_florent_: Preserves the old method and allows the new method...07:30
_florent_mithro: yes probably, i haven't look closely yet :) will do!07:30
mithro_florent_: Should have thought about telling xobs to use the sim target...07:33
_florent_scanakci: using a frequency that is too low can indeed cause issues for the DDR3 calibration. We have some limitation with the IDELAYE2/ODELAYE2 taps for write/read leveling07:34
mithro_florent_: After building that etherbone example I linked above, Ethernet seems to come up but I don't get any arp response or response to ping07:36
mithro_florent_: Can the libuip interfere with the hardware etherbone?07:38
_florent_scanakci: i would recommend using the max sys_clk_freq you can that don't produce timing violations, the Kintex7 is quite capable so should be able to run your CPU at a higher frequency07:39
mithroIE Should I remove these? https://github.com/mithro/litex-buildenv/blob/4f7b1b37531fe5f0773cf737b4e1b57d6d775165/targets/arty/etherbone.py#L38-L4007:41
tpbTitle: litex-buildenv/etherbone.py at 4f7b1b37531fe5f0773cf737b4e1b57d6d775165 · mithro/litex-buildenv · GitHub (at github.com)07:41
_florent_mithro: for now, you can't connect LiteEthPHY to LiteEthMAC and LiteEthUDPIPCore, you have to choose07:43
mithro_florent_: I need to give LiteEthUDPIPCore a LiteEthPHY right?07:44
_florent_yes or remove the LiteEthMAC07:45
_florent_mithro: here is an Etherbone example: https://github.com/enjoy-digital/usb3_pipe/blob/master/kc705.py#L95-L12007:46
tpbTitle: usb3_pipe/kc705.py at master · enjoy-digital/usb3_pipe · GitHub (at github.com)07:46
mithro_florent_: We should probably have an arty example of etherbone somewhere that is easy to find07:52
_florent_mithro: yes i also realized that07:53
mithroDoah! I configured IP address of 192.168.1.50 and have been trying to ping 192.168.100.50 ...08:03
_florent_is it working now?08:09
mithro_florent_: Still no luck :-/08:17
mithro_florent_: This is what I have now -> https://github.com/mithro/litex-buildenv/blob/3d2e45db21254fe40e6797262da7bf713ac4e561/targets/arty/etherbone.py#L27-L5608:18
tpbTitle: litex-buildenv/etherbone.py at 3d2e45db21254fe40e6797262da7bf713ac4e561 · mithro/litex-buildenv · GitHub (at github.com)08:18
mithro_florent_: The link is up, but I'm not seeing any arp responses08:18
_florent_mithro: ok i need to have a closer look. I tested if on others targets recently but not on Arty08:19
xobsIs there any documentation on how to use litex_sim?  I'm having to patch Makefiles to add `-I/opt/miniconda3/include` and `-L/opt/miniconda3/lib`, and I feel that's the wrong way to do it.08:23
_florent_xobs: litex_sim is simular to others designs, just that it uses Verilator as a backend for the simulation08:28
_florent_xobs: so you just need to install Verilator + libevent-dev libjson-c-dev (on Ubuntu)08:29
xobs_florent_: I see.  I had to patch a bunch of files to add the miniconda3 include and library files, and now it's asking me for my password.08:29
xobsDoes this use tun/tap, then?08:29
_florent_xobs: this is explained in: https://github.com/enjoy-digital/litex#quick-start-guide-for-advanced-users08:29
tpbTitle: GitHub - enjoy-digital/litex: Build your hardware, easily! (at github.com)08:29
_florent_when adding ethernet, it request the password yes to create the ethernet tap08:30
xobsI see.  Then this won't work under WSL :(08:30
_florent_but for a first test, you can just execute litex_sim08:30
xobsWith my patches, I get a teminal.  Yay!08:31
xobsBut TUN isn't implemented under WSL :(08:32
_florent_xobs: in fact we are using https://github.com/enjoy-digital/tapcfg08:33
tpbTitle: GitHub - enjoy-digital/tapcfg: tapcfg (at github.com)08:33
_florent_xobs: so it should work with WSL08:33
_florent_but not sure i tested08:34
xobs`Error opening device /dev/net/tun: No such file or directory`08:35
_florent_too bad, litex_sim would have been very useful for adding ethernet support to wishbone-tool08:38
_florent_xobs: What's your prefered board to test Etherbone? NeTV2? i could prepare a design for it if you want08:39
xobsI'm at LCA, and Tim has an Arty here that's easiest to test with.08:41
mithro_florent_: I'm probably doing something stupid with this arty config08:45
mithroI managed to just get one reply then...08:50
mithro18:46:28.510005 ARP, Reply 192.168.1.50 is-at 10:e2:d5:00:00:00 (oui Unknown), length 4608:50
*** CarlFK has quit IRC13:31
*** CarlFK1 has joined #litex14:05
*** flammit has quit IRC17:34
*** flammit has joined #litex17:35
*** scanakci has quit IRC18:31
*** sorear has quit IRC18:31
*** key2 has quit IRC18:32
*** mithro has quit IRC18:32
*** _florent_ has quit IRC18:32
*** daveshah has quit IRC18:32
*** flammit has quit IRC18:32
*** key2 has joined #litex18:33
*** _florent_ has joined #litex18:34
*** sorear has joined #litex18:36
*** daveshah has joined #litex18:38
*** mithro has joined #litex18:39
*** _florent_ has quit IRC18:42
*** sorear has quit IRC18:42
*** sorear has joined #litex19:00
*** sorear has quit IRC19:08
*** _florent_ has joined #litex20:36
*** CarlFK1 has quit IRC21:14
*** futarisIRCcloud has quit IRC21:31
*** CarlFK has joined #litex22:48
*** flammit has joined #litex23:29

Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!