| *** tpb has joined #litex | 00:00 | |
| *** CarlFK has quit IRC | 00:18 | |
| *** _whitelogger has quit IRC | 01:40 | |
| *** _whitelogger has joined #litex | 01:43 | |
| somlo | _florent_: re. endianness, that was a good idea, so I replicated your experiment by diff-ing the dut.v generated by litex_sim.py for vexriscv and mor1kx | 15:06 |
|---|---|---|
| somlo | and you're right, there's nothing different at all except for the actual CPU module being linked into the design | 15:07 |
| somlo | is it possible that endianness as we see it with the 'mr' command (one byte at a time) is simply a result of how the CPU data pins are connected to the rest of the surrounding verilog? | 15:09 |
| somlo | i.e. of how they're exposed by the CPU's internal wiring? | 15:10 |
| _florent_ | somlo: i also think it's just how data are organized on the interface for big/little endian architectures, here is test with vexriscv vs lm32: | 18:05 |
| _florent_ | https://gist.github.com/enjoy-digital/064e7f93d0eb783941db6848f6b41ea3 | 18:05 |
| tpb | Title: gist:064e7f93d0eb783941db6848f6b41ea3 · GitHub (at gist.github.com) | 18:05 |
| somlo | _florent_: ok, I'll write something up about this in issue #314; also, I would like to have memcpy-"like" functionality for >64 CSRs that "just works" regardless of cpu endianness, and knowing where/why the bytes are flipped was a precondition to even beginning to think about that :) | 18:19 |
| _florent_ | ok thanks | 18:19 |
| somlo | _florent_, daveshah: unrelated to CSRs, I'm trying to get litesdcard to work on the trellisboard, and I just realized the SDPHYIOS are specific to the FPGA, and currently only Xilinx is supported (https://github.com/enjoy-digital/litesdcard/blob/master/litesdcard/phy.py#L637) | 18:21 |
| tpb | Title: litesdcard/phy.py at master · enjoy-digital/litesdcard · GitHub (at github.com) | 18:21 |
| somlo | is there anything already in the works for ecp5/trellisboard? | 18:21 |
| _florent_ | somlo: not yet, but i could help. Since the Nexys4DDR has a SD Card slot, maybe you should first test things on it, then switch to the trellisboard. | 18:24 |
| somlo | yeah, on nexys4ddr it should be "xc7", for which we already have SDPHYIOS7 | 18:27 |
| somlo | I'm guessing it's a matter of figuring out what the ECP5 equivalent of "IBUFG" and "IDDR[2]" blocks are, and instantiating them instead :) | 18:31 |
| daveshah | The IBUFG shouldn't be needed at all as it will be promoted anyway | 18:32 |
| daveshah | The IDDR equivalent is IDDRX1F | 18:32 |
| somlo | daveshah: thanks! so, just assign the clkfb pad directly to sd_fb, and fiddle around some with IDDRX1F | 18:34 |
| daveshah | Yeah | 18:35 |
| somlo | I'll do what _florent_ said and get something working on nexys4ddr first, so I know it's not some unrelated stupid thing I did when it won't work on the trellisboard, then I'll take a stab at an ECP5 SDPHYIO, unless somone pre-empts me before then :) | 18:35 |
| somlo | _florent_: if I'm guessing right, litesdcard ignores the "card_detect" pin, is that correct? (https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/reference-manual#microsd_slot) | 21:05 |
| tpb | Title: Nexys 4 DDR Reference Manual [Reference.Digilentinc] (at reference.digilentinc.com) | 21:05 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!