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| futarisIRCcloud | https://github.com/lawrie/saxonsoc-ulx3s-bin/blob/master/linux/u-boot/README.md | 12:28 |
|---|---|---|
| tpb | Title: saxonsoc-ulx3s-bin/README.md at master · lawrie/saxonsoc-ulx3s-bin · GitHub (at github.com) | 12:28 |
| keesj | Banana Memory Bus? | 14:12 |
| keesj | is the full soc written in SpinalHDL ? | 14:12 |
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| _florent_ | keesj: yes the SoC is probably written in SpinalHDL, i remember discussing with @Dolu of Banana Memory Bus, IIRC it's a kind of simplified AXI with 2 channels | 14:55 |
| _franck_ | q | 15:24 |
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| keesj | Interesting. I also talked to somebody last week who is doing mostly myhdl the idea for the project looks quite similar to migen. The syntax is a bit different . the thing I see here is that there is activity around it and that I quite like. | 18:54 |
| keesj | is appears also that litex/migen has more/better integration (tools , building soc capabilities) | 18:55 |
| somlo | https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/include/hw/common.h#L19 | 21:23 |
| tpb | Title: litex/common.h at master · enjoy-digital/litex · GitHub (at github.com) | 21:23 |
| somlo | if 'b' is 8 bits, 'w' is 16, and 'l' is 32, then what should 64 be ? :) | 21:23 |
| somlo | _florent_: ^^^ | 21:24 |
| somlo | maybe if 32 were 'd', we could call 64 'q'... | 21:26 |
| _florent_ | somlo: good question :) maybe we should just give more explicit names like csr_write_8b, csr_write_16b, ... | 22:06 |
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