Wednesday, 2019-11-06

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somlo_florent_: wait, I could use LiteDRAMNativePortConverter to expose an "appropriately" sized LiteDRAM port in soc_sdram?21:35
somloIn that case, maybe I should redo and force-push https://github.com/enjoy-digital/litex/pull/300 to use that instead of switching everything to wishbone and converting there ?21:36
tpbTitle: RFC: Direct link between Rocket/mem_axi <--> LiteDRAM dataport by gsomlo · Pull Request #300 · enjoy-digital/litex · GitHub (at github.com)21:36
somloin other words, instead of "mem_axi <-> mem_wb <-> wb_converter <-> litedram_wb <-> litedram_native"21:38
somloI could do "mem_axi <-> litedram_axi <-> litedram_converter <-> litedram_native"... Maybe this latter one would be more efficient?21:39
somloit's for the "fallback" case when there's no variant of a cpu with a mem_axi width matching the available litedram default port width21:40
somlo_florent_: I finally get it, line 312 is when port.mode is "both", and we'd obviously need that to work before anything I just said (above) would make sense22:25
somlosorry, had a long day afk and now trying to find two remaining brain cells to rub together :) :)22:25
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