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| somlo | _florent_: so far, reverting 1425a68 isn't getting me noticeably better Fmax numbers, so I don't think it's the culprit either | 01:36 |
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| somlo | guess it's karma for having gotten so many good runs with fmax at 60MHz earlier on :) | 01:37 |
| somlo | guess I'll just start some builds in a loop on a different server and forget about them | 01:38 |
| somlo | use nexys5ddr to refine my AXI-point-to-point rocket-litedram link, then start working on getting it all to run on the Trellis board | 01:39 |
| somlo | that one has enough room for me not to need '-nowidelut', which should hopefully get me past 60MHz more often | 01:40 |
| somlo | *nexys4ddr :) | 01:40 |
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| acathla | How do I make litex generate the csr.csv I need? | 14:53 |
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| acathla | Found it, but doesn't communicate :( | 15:04 |
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| _florent_ | acathla: are you trying to use a uart <--> wishbone bridge? If so maybe you can have a look at: https://github.com/litex-hub/fpga_101/tree/master/lab003 | 16:15 |
| tpb | Title: fpga_101/lab003 at master · litex-hub/fpga_101 · GitHub (at github.com) | 16:15 |
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| somlo | _florent_: I'm currently connecting Rocket's axi port directly to LiteDRAM: https://pastebin.com/t2aBuWFA | 18:11 |
| somlo | _florent_: but obviously Rocket issues addresses starting at 0x8000_0000, and I would guess LiteDRAM expects addresses to start at 0 | 18:12 |
| somlo | wondering if there's an easy way to tell LiteDRAM to expect the offset. | 18:13 |
| somlo | right now it works, because we have less than 0x8000_0000 bytes of RAM, so the MSB is discarded :) | 18:13 |
| somlo | but if we ever had more than 2Gig, it'd be a problem | 18:13 |
| somlo | here's a slightly more streamlined version (add memory region only, no "dangling" wishbone slave port): https://pastebin.com/5v8QPSGU | 18:33 |
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| _florent_ | somlo: thanks, i'll look at that tomorrow | 20:48 |
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| somlo | _florent_: thanks! it's not commit-ready or anything, just looking for the most elegant way to introduce an offset into a connection between two interfaces | 21:48 |
| somlo | I think for wishbone it's done by some combo of mem_decoder() and the Decoder class in interconnect/wishbone.py, still trying to mentally track the logic flow and where the translation actually happens when main_mem is a wb slave in the "classic" setup :) | 21:49 |
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