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| _florent_ | scanakci: can you do a pull request on litex for your simulations changes? | 07:13 |
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| somlo | _florent_: re. commit #ca81cc20, is it really necessary to check width here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_core.py#L189 ? After all, if data width is equal, Converter will simply hook them up without any added logic: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/wishbone.py#L489 | 12:31 |
| tpb | Title: litex/soc_core.py at master · enjoy-digital/litex · GitHub (at github.com) | 12:31 |
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| somlo | very hacky first-pass experiment connecting LiteDRAM directly to Rocket's cached mem_axi port: https://pastebin.com/1rQzE1kt | 14:52 |
| somlo | at 75MHz on the nexys4ddr, coremark went from 35 to 48 (was honestly hoping for more of a bump than that, but maybe it's because I threw away the L2 cache in the process) | 14:54 |
| somlo | running nbench (which takes a LOT longer) to get more specifically memory-oriented measurements | 15:05 |
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| scanakci | somlo: Did you try simulating the Rocket with up-to-date litex? | 17:00 |
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| scanakci | I am getting "ImportError: cannot import name 'LiteDRAMCore'" currently. I was wondering if I messed up something. | 17:01 |
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| scanakci | ignore please, it works fine after updating the other modules | 17:10 |
| scanakci | i.e litedram | 17:10 |
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| _florent_ | somlo: indeed, we can simplify the automatic width adaptation, i'll do that | 18:05 |
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| y2kbugger | Working on adding iceFUN board to buildenv. No problems with gateware+bios+none using lm32 but when switching to vexriscv I can't hit bios. Tim suggested wishbone I seem to be able to peek but it's intermittent. | 19:14 |
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