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| shenki | hello! i am attempting to boot linux on vexriscv in verilator, and it has been sitting on "--========== Booting Linux =============--" for several minutes | 00:07 |
|---|---|---|
| shenki | is there a way to see what is going on under the hood? | 00:07 |
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| xobs | john_k: I didn't include Python because I assume the user has a Python on their system already. If I were to include a Python I'd want one statically linked against musl at least. | 01:02 |
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| guan | has anyone here gotten linux-on-litex-vexriscv working on the versa ecp5 board? using the prebuilt bitstream, my lxterm says "[LXTERM] Starting...." and then stops | 01:19 |
| guan | i'm on a mac, i can get blinky and other stuff working on the board fine, and it says "svf file programmed successfully"; there are two tty's associated with the FTDI chip, i'm using the first one | 01:20 |
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| shenki | guan: i'm trying to get the same going on arty | 02:27 |
| guan | shenki: oh that reminds me, i also tried on an arty, same result iirc :-) | 02:27 |
| guan | the README says speed is 1e6 (1 MHz?), I wonder where to check if that’s correct | 02:28 |
| shenki | yeah. iw wonder when this last worked | 02:38 |
| shenki | _florent_: when did you last have the vexriscv linux booting? | 02:38 |
| CarlFK | it worked when I gave a talk https://chicagolug.org/meetings/2019-07-13/ | 02:59 |
| tpb | Title: July 2019 Meeting of ChicagoLUG (at chicagolug.org) | 02:59 |
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| shenki | guan: I got it to work just now, using linux-on-litex-vexriscv and the prebuild kernel/dtb/rootfs | 03:21 |
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| futarisIRCcloud | shenki: Have you tried with a kernel / dtb / rootfs that you built on your system? | 03:54 |
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| shenki | uroot@buildroot:~# uname -a | 04:45 |
| shenki | Linux buildroot 5.0.13 #1 Tue Sep 17 22:24:09 ACST 2019 riscv32 GNU/Linux | 04:45 |
| shenki | root@buildroot:~# dmesg |head | 04:45 |
| shenki | [ 0.000000] No DTB passed to the kernel | 04:45 |
| shenki | [ 0.000000] Linux version 5.0.13 (joel@voyager) (gcc version 8.3.0 (Buildroot 2019.11-git-00298-g5c9e9ef10087)) #1 Tue Sep 17 22:24:09 ACST 2019 | 04:45 |
| shenki | futarisIRCcloud: yes! | 04:45 |
| futarisIRCcloud | Cool | 04:50 |
| shenki | does someone have a git tree with the linux kernel patches? | 05:03 |
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| _florent_ | shenki: i think you had an issue with emulator.bin, i need to add compilation of emulator when building the board | 05:27 |
| _florent_ | shenki: i'll try to do that now, otherwise, i'm using linux-on-litex-vexriscv regularly to check we don't have regressions on LiteX and the cores | 05:30 |
| _florent_ | guan: maybe you can give a try on the versa/arty with the prebuilt bistreams/images: https://github.com/litex-hub/linux-on-litex-vexriscv-prebuilt | 05:31 |
| tpb | Title: GitHub - litex-hub/linux-on-litex-vexriscv-prebuilt: Prebuilt bitstreams / linux images for litex-on-litex-vexriscv repository (at github.com) | 05:31 |
| _florent_ | guan: just to verify everything is correct on the hardware side | 05:32 |
| _florent_ | guan: when the bitstream is loaded and you open litex_term, you should be able to interact with the bios | 05:33 |
| shenki | _florent_: ok. I have the hardware working now, so that looks good for testing | 05:48 |
| shenki | _florent_: i rebased the linux patches on 5.3 and it fails to boot. it looks like with the 5.0 kernel it wasn't getting a dtb, but it is with 5.3? https://gist.github.com/shenki/3dcf7829efef7cc1d8e3a7ca065d9045 | 05:48 |
| tpb | Title: linux 5.3 on vexriscv on arty · GitHub (at gist.github.com) | 05:48 |
| shenki | here's the working boot: https://gist.github.com/shenki/8eb53fbcf5658440f2deb8e98761fc81 | 05:49 |
| tpb | Title: linux 5.0 on vexriscv on arty · GitHub (at gist.github.com) | 05:49 |
| _florent_ | shenki: i saw the warning on linux 5.0, but the behaviour was clearly different depending the dtb i was providing, so even if there is a warning, the kernel seems to use the dtb | 05:52 |
| shenki | okay | 05:54 |
| _florent_ | shenki: i know we had issues with linux 5.1: https://github.com/litex-hub/linux-on-litex-vexriscv/pull/20 | 05:56 |
| tpb | Title: force buildroot commit rev to 982a61b6adabbcd68a0eb9ad1e348a732915e9e4 by futaris · Pull Request #20 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 05:56 |
| shenki | ok. that looks buildroot/userspace related | 05:58 |
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| shenki | _florent_: do we have a watchdog or something that can reset the CPU? | 06:18 |
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| shenki | being able to type 'reboot' and have it reset the CPU would be handy :) | 06:18 |
| _florent_ | shenki: there is a CSR to reset the cpu yes, and was also thinking about adding reboot support: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/45 | 06:30 |
| tpb | Title: Add reboot support · Issue #45 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 06:30 |
| _florent_ | if you know how to do that in linux, here we just need to write 1 to CSR_CTRL_RESET_ADDR to reboot the CPU | 06:31 |
| shenki | Oh, we have that in hardware already? | 06:32 |
| shenki | I can write the linux driver for it | 06:32 |
| _florent_ | yes it's already there :) | 06:33 |
| shenki | _florent_: cool. how do we make it show up in the device tree? | 06:33 |
| _florent_ | i can add it if you tell me what structure need to be added to the device tree for that | 06:34 |
| futarisIRCcloud | https://www.kernel.org/doc/Documentation/devicetree/bindings/reset/reset.txt | 06:36 |
| shenki | that's the wrong kind of reset | 06:36 |
| daveshah | guan: you want to use the second tty on the Versa for serial comms, the first is for programming | 06:36 |
| shenki | that subsystem is about reset lines for IP blocks | 06:36 |
| shenki | for when you have a GPIO that keeps a bit of IP in reset when it's not being used | 06:37 |
| futarisIRCcloud | Whoops. :P | 06:37 |
| shenki | you are not the first person to make that assumption | 06:38 |
| shenki | it looks like there are a pair of drivers that do use it for resetting the CPU | 06:38 |
| shenki | register_restart_handler is where lots of SoCs register their reboot handler | 06:39 |
| shenki | lots appear to put their driver in drivers/power/reset | 06:39 |
| _florent_ | shenki: in case you want to customize the .dts for that, in json2dts.py, you will get the csr reset address for the CPU with: d["csr_registers"]["ctrl_reset" ]["addr"] | 06:45 |
| shenki | cool. I'll cook up a patch | 06:46 |
| _florent_ | great, thanks! | 06:52 |
| shenki | _florent_: can we use gdb on the host to debug code on the FPGA? | 06:56 |
| _florent_ | shenki: i've not used it (yet), but i know others are using it, xobs created a tool for that: https://github.com/xobs/wishbone-utils | 06:59 |
| tpb | Title: GitHub - xobs/wishbone-utils: Utilities for working with a Wishbone bridge (at github.com) | 06:59 |
| shenki | ah. mithro was telling me about this the other day | 07:00 |
| shenki | do I need to add something to the hardware design? | 07:01 |
| _florent_ | but to use it, you will need to use linux+debug variant instead of linux: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py#L55 | 07:01 |
| tpb | Title: linux-on-litex-vexriscv/soc_linux.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 07:01 |
| _florent_ | yes ^ :) | 07:02 |
| shenki | :D | 07:02 |
| xobs | shenki: You can use the uart bridge, USB bridge, SPI bridge... basically any bridge ought to work. | 07:02 |
| shenki | hey xobs. i am on the arty, so i'll try uart to start with | 07:03 |
| xobs | Sure. Just enable the bridge, map the debug region, and run "wishbone-tool -u [/dev/serial-port] -s gdb" | 07:04 |
| _florent_ | shenki: since the uart is already used by linux, maybe it would be easier to use a USB<-->Serial module on a PMOD and do a UART wishbone bridge with it | 07:04 |
| xobs | You might also want to add "--bind-addr 0.0.0.0" if you're debugging it from a different machine. | 07:04 |
| shenki | xobs: okay | 07:05 |
| xobs | wishbone-tool binaries are at https://github.com/xobs/wishbone-utils/releases/latest -- though I've never had the occasion to test the s390x versions. | 07:06 |
| tpb | Title: Release v0.3.2: travis: disable tests on ppc64le · xobs/wishbone-utils · GitHub (at github.com) | 07:06 |
| shenki | that is amusing. i wonder if i could find a machine on the work network to test them with | 07:06 |
| shenki | _florent_: do you have a snippet for soc_linux.py to use a pmod? | 07:08 |
| xobs | shenki: I'm not sure about _florent_, but I'd imagine pmod is a Connector, which i haven't found any good documentation on. | 07:10 |
| xobs | I did, however, manage to get it working here: https://github.com/im-tomu/foboot/blob/foboot-2/hw/foboot-bitstream.py#L189 | 07:11 |
| tpb | Title: foboot/foboot-bitstream.py at foboot-2 · im-tomu/foboot · GitHub (at github.com) | 07:11 |
| xobs | ... and https://github.com/im-tomu/foboot/blob/foboot-2/hw/foboot-bitstream.py#L577 | 07:11 |
| tpb | Title: foboot/foboot-bitstream.py at foboot-2 · im-tomu/foboot · GitHub (at github.com) | 07:11 |
| xobs | And I'd imagine the uart is somewhat similar. | 07:11 |
| _florent_ | shenki: i'm preparing a patch for soc_linux to add a UART wishbone bridge | 07:11 |
| shenki | thanks | 07:12 |
| shenki | xobs: I'm intrigued by RandomFrimwareROM. What did you do there? | 07:13 |
| xobs | shenki: I filled the ROM with random data, then as part of `fomu-flash` I look for that data and replace it on the fly. | 07:14 |
| xobs | It's similar to what `icebram` does. I think xilinx has similar options. | 07:14 |
| xobs | If you want to bundle the software in the image itself, it's very handy. Litex seems to prefer having a bios that calibrates DDR, and then stores firmware XIP on SPI following the bitstream image. | 07:15 |
| shenki | so it gives you a magic number to search and replace with the actual firmware image? | 07:16 |
| xobs | Correct. If it was something like all zeroes or ones, or a repeating pattern, you wouldn't know which bits of the input file you're looking at. | 07:20 |
| _florent_ | shenki: here is how to add the a serial bridge on pmod: https://hastebin.com/oruzulinud.rb | 07:25 |
| _florent_ | shenki: just change tx/rx mapping to what is used on your pmod | 07:26 |
| _florent_ | before trying gdb with it you can try to access some CSRs or Wishbone regions with wishbone-tool | 07:27 |
| xobs | Yeah, depending on your mapping you can examine ROM data by looking at offset 0. | 07:33 |
| shenki | ok, thanks | 07:37 |
| xobs | Oh, I thought triple quotes """ in Python trimmed whitespace, but I guess that's not true by default. (Currently trying to do something with the CSRField documentation) | 07:42 |
| xobs | I suppose that's fine if it gets passed to Markdown, which will reformat it anyway. | 07:44 |
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| _florent_ | xobs: i was also thinking about that. Keeping the whitespace allow the code to be clean, but is maybe not convenient for the documentation. If the documentation can handle that that would be nice. | 08:28 |
| xobs | florent: Markdown shouldn't care, so let's keep it like it is. | 08:28 |
| mithro | Textwrap.deindent | 09:14 |
| kgugala | hi all | 09:20 |
| kgugala | xobs: We have released the first version of USB test suite based on your work in valentyusb | 09:21 |
| kgugala | xobs: you can take a look on this here https://github.com/antmicro/usb-test-suite-build | 09:22 |
| tpb | Title: GitHub - antmicro/usb-test-suite-build (at github.com) | 09:22 |
| xobs | kgugala: Oh wow. Cool! | 09:22 |
| kgugala | xobs: please take a look and comment/open issues | 09:22 |
| kgugala | xobs: right now we want to make this more generic so more IPs can be tested + we want to add enumeration tests | 09:24 |
| kgugala | xobs: like full enumeration process in different OSes | 09:24 |
| xobs | That's huge. | 09:24 |
| xobs | I always tell people to test with Windows, because it's always the pickiest. But if that can be codified that's even better. | 09:25 |
| kgugala | It will be some work, but I think useful | 09:25 |
| futarisIRCcloud | kgugala: Looks good. | 09:28 |
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| _florent_ | kgugala: nice | 09:40 |
| john_k[m] | xobs: understood re: python in tool chain. I raised the issue since it was there in 1.3 but missing in later builds | 09:56 |
| john_k[m] | Will re-test a bit today | 09:56 |
| xobs | Here's a first draft of what I have in mind for generating reference manuals: https://doctest.xobs.io/timer.html | 11:34 |
| tpb | Title: TIMER0_LOAD3 doctest documentation (at doctest.xobs.io) | 11:34 |
| xobs | It needs more documentation around the modules themselves, and probably could use a reference table up top. And more vertical space. | 11:35 |
| xobs | But the idea is there! | 11:36 |
| xobs | It has real address offsets, field tables, and multiple csr types. I just only had the one timer module in the system. | 11:42 |
| guan | daveshah _florent_: ah thanks, i just tried the second tty with same results, it just gets stuck at "[LXTERM] Starting...". nothing else shows up (even after i hit enter). this is using the prebuilt bitstream. i'll try from a linux box later. | 11:49 |
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| guan | i should dig out the logic analyzer and see what's actually going across the uart pins | 14:18 |
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| daveshah | xobs: those autogenerated docs are very nice! | 16:08 |
| daveshah | guan: yeah, could be an odd baud rate issue or something | 16:08 |
| guan | daveshah: is soc_linux.py:56 the only place i have to change to make it slower? (+ the command line argument for lxterm) | 16:11 |
| daveshah | I think that's it | 16:12 |
| somlo | mithro: re. PR 260, Rocket has a built-in L1 cache, so arguably it might be worth spending fpga bram on just making that bigger, instead of also having a LiteX l2 in front of the sdram controller | 16:29 |
| somlo | if I'm not mistaken, l2 is the *only* cache for most of the 32-bit CPUs LiteX supports, there is no L1 on any of them (might be wrong about that, appreciate someone kicking me if that's the case :) | 16:30 |
| mithro | somlo: The L2 cache is shared between DMA controllers and the CPU, which can be good / can be bad depending on time | 16:30 |
| mithro | kgugala / xobs: Did you see https://github.com/JohnDMcMaster/usbrply ? Convert a .pcap file (captured USB packets) to Python or C code that replays the packets in the .pcap file | 16:31 |
| tpb | Title: GitHub - JohnDMcMaster/usbrply: Replay USB messages from Wireshark (.cap) files (at github.com) | 16:31 |
| mithro | Done by a person who was on my team a while back but I totally didn't know about it until 2 days ago | 16:31 |
| somlo | ok, so I have to understand how dma will fit into my plan of just connecting the SDRAM data path to the appropriate rocket axi master port | 16:31 |
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| _florent_ | xobs: sorry just back but i really like the generated documentation | 19:22 |
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| somlo | _florent_: re. litedram commit d93dded, may I suggest printing the actual values of the mismatched width values: https://pastebin.com/UzETkgqT | 19:45 |
| tpb | Title: [Diff] diff --git a/litedram/frontend/wishbone.py b/litedram/frontend/wishbone.py inde - Pastebin.com (at pastebin.com) | 19:45 |
| somlo | and thanks for the explanation re. l2_cache as an alternative "UpConverter" :) | 19:47 |
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