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| futarisIRCcloud | Cool. | 03:13 |
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| xobs | Is there a SPI slave device available anywhere? | 05:57 |
| xobs | I know it shouldn't be too difficult to create one from scratch, but the clock recovery scares me a little bit and it would be nice to have an existing solution. | 05:57 |
| futarisIRCcloud | xobs: https://github.com/osresearch/spispy/blob/master/spi_device.v ? | 06:07 |
| tpb | Title: spispy/spi_device.v at master · osresearch/spispy · GitHub (at github.com) | 06:07 |
| xobs | futarisIRCcloud: nice find! | 06:08 |
| xobs | Some background: I use wishbone-over-USB for debugging, but now I'm having issues with USB enumeration, so I'd like to come up with wishbone-over-SPI. | 06:08 |
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| _florent_ | xobs: hi, here is somehing i was using a few years ago to control a CSR bus over SPI: https://hastebin.com/idivomeqej.pl (sys_clk is expected to be faster than spi_clk, x4 or more should be fine) | 06:29 |
| xobs | _florent_: wow, you've got a lot of fun projects tucked away. | 06:30 |
| xobs | Mind if I adapt that to work with full Wishbone? | 06:31 |
| _florent_ | xobs: sure, in fact i was planning to reuse it to add SPI Slave in LiteX but haven't been able to work on that yet | 06:35 |
| _florent_ | i was thinking about adding SPISlave to https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/spi.py | 06:35 |
| tpb | Title: litex/spi.py at master · enjoy-digital/litex · GitHub (at github.com) | 06:35 |
| _florent_ | and then it could be reused to do SPISlave to Wishbone by module that would just handle the wishbone protocol | 06:36 |
| _florent_ | i can try to add do the initial SPISlave if you want, then you could the wishbone protocol part? | 06:38 |
| xobs | _florent_: sure. I'm not sure the best way to create a SPI master, really. | 06:39 |
| xobs | My approach was just to bit-bang it on a Raspberry Pi, which severely limits where you can run it. | 06:40 |
| xobs | How do people normally interact with SPI devices? | 06:40 |
| _florent_ | just to be sure i understand correctly, you want the SPI in the FPGA to be a slave, so that you can do the equivalent of your USB wishbone bridge? | 06:41 |
| xobs | _florent_: correct. Normally people would use a uart, but I don't have the space to fit a uart in there. | 06:43 |
| _florent_ | xobs: in most of the project i did, SPI was used as master, that's why slave is not there | 06:45 |
| xobs | That makes sense. It's kind of specialized. | 06:47 |
| _florent_ | xobs: i added a minimal SPISlave: https://github.com/enjoy-digital/litex/commit/41fe7cae0b5341531f609943d5f70afd6256cfc8 | 08:07 |
| tpb | Title: core/spi: add minimal SPISlave · enjoy-digital/litex@41fe7ca · GitHub (at github.com) | 08:07 |
| _florent_ | xobs: but i'm not sure it's really convenient to use since full miso is sampled at the beginning of the transfer | 08:08 |
| _florent_ | basically, when cs_n is set low, you receive self.start is asserted | 08:09 |
| _florent_ | if self.mosi is not set, user has then to set it the cycle self.start is received | 08:10 |
| _florent_ | (sorry, self.miso) | 08:11 |
| _florent_ | when the transfer ends (cs_n is set high), self.done is set and self.mosi can be used | 08:11 |
| xobs | _florent_: cool! | 08:11 |
| xobs | I'm still working from your previous example -- https://github.com/xobs/spibone/blob/master/spibone.py | 08:12 |
| tpb | Title: spibone/spibone.py at master · xobs/spibone · GitHub (at github.com) | 08:12 |
| _florent_ | self.loopback can be use to do some initial testing | 08:12 |
| _florent_ | ok nice, it will maybe be easier to get it done this way, even if you don't use it, SPISlave will still be useful for others things | 08:15 |
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| John_K | any pointers how to figure out what the righ IOSTANDARD is here? ISE 14.7 (Win 10 edition) with Spartan6 ERROR:NgdBuild:488 - Attribute value "DIFF_SSTL18_DCI" is not an accepted value for attribute "IOSTANDARD" on "ddram_clock_p". | 18:24 |
| John_K | I get the same for "SSTL18_DCI" on the rest of the ddram signals | 18:24 |
| John_K | I'm fairly new to DDR interfaces and IO standards and am cribbing from other implementations | 18:25 |
| daveshah | I suspect for Spartan 6 you need to remove the _DCI | 18:26 |
| John_K | "SSTL18" had originally given me errors, I guess I'll give "SSTL18_I" a shot | 18:28 |
| daveshah | You need the _I (there are always two types of SSTL - I and II, I can't remember the exact difference but I think it's drive strength or something) | 18:29 |
| John_K | aha, thanks | 18:29 |
| daveshah | You're working on the Pano Logic, right? | 18:29 |
| John_K | G2, yes | 18:29 |
| daveshah | Interested to see how that works out | 18:30 |
| daveshah | Could be a very nice platform | 18:30 |
| John_K | thanks! | 18:30 |
| John_K | Yeah, apparently there is a way to update the SPI over the network using stock firmware | 18:30 |
| John_K | that could be a huge help for provisioning units without opening them | 18:30 |
| John_K | "SSTL18_I" made ngdbuild happy | 18:37 |
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| _florent_ | John_K: if the memory is a DDR2, you should look at the Atlys board | 20:36 |
| _florent_ | DDR2DQ6 | 20:36 |
| _florent_ | oops | 20:36 |
| _florent_ | https://github.com/timvideos/litex-buildenv/blob/master/platforms/atlys.py#L220-L302 | 20:36 |
| tpb | Title: litex-buildenv/atlys.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 20:36 |
| _florent_ | and | 20:37 |
| _florent_ | https://github.com/timvideos/litex-buildenv/blob/master/targets/atlys/base.py | 20:37 |
| tpb | Title: litex-buildenv/base.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 20:37 |
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| mithro | hey John_K - did we meet at CCCamp19? | 21:43 |
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| John_K | _florent_: aha thanks, I think I looked at a combination of mimasv2 and minispartan6 | 22:06 |
| John_K | mithro: we did not, I did some Cypress FX firmware loading stuff a year or two ago though | 22:06 |
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| mithro | John_K: What made you decide to start hacking on RISC-V for the Pano Logic? | 22:20 |
| mithro | John_K: I noticed that your in the bay area? I am also... | 22:21 |
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| futarisIRCcloud | John_K: I'll be in the bay area next week too. | 22:58 |
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