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| futarisIRCcloud | https://youtu.be/Ir_KBgbVr58 | 07:34 |
|---|---|---|
| _florent_ | mithro: thank, i was thinking about having a zephyr-on-litex-vexriscv repo in litex-hub similar to the linux one to show how to setup/use it. | 07:52 |
| _florent_ | futarisIRCcloud: thanks for the link | 07:53 |
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| olofk | Hi there | 09:47 |
| olofk | Anyone familiar with litesdcard? Looking for some hand-holding | 09:48 |
| keesj | Hi there | 10:09 |
| keesj | olofk: I have a little (tested it somewhat) | 10:10 |
| olofk | keesj: Cool. On which hw? | 10:10 |
| keesj | on the arty board with a self made adapter | 10:11 |
| olofk | ah ok. That should be pretty similar to my Nexys A7 | 10:12 |
| keesj | like this https://i.imgur.com/hlyKF3e.jpg | 10:13 |
| olofk | So, the thing I want to do is to generate a stand-alone core that I can integrate into my SoC. (No, it's not a Litex-based SoC). Struggling a bit with Migen syntax. | 10:14 |
| olofk | Nice board :) | 10:14 |
| keesj | you core also uses migen or is it something else? | 10:15 |
| olofk | litesdcard is written in migen | 10:15 |
| olofk | Rest of the SoC (except for a LiteDRAM instantiation) is verilog | 10:16 |
| olofk | So as the first step I want to bring out the litesdcard stream ports to the top of the generated verilog. Think I got the sink port done and the source port should be similar, but I have no real idea about what else I need to expose | 10:17 |
| keesj | do you implement a bus like wishbone? | 10:17 |
| olofk | For configuration it will likely be axi or apb. For the stream ports I intend to do a stand-alone stream-to-axi converter. Got one for wb that I think I can modify (https://github.com/olofk/wb_streamer) | 10:19 |
| tpb | Title: GitHub - olofk/wb_streamer: Wishbone component for converting data streams to wishbone transactions (at github.com) | 10:19 |
| keesj | I think that is the kind of interfacing you will need | 10:19 |
| olofk | What kinds of bus interface slave interfaces can I generate with litex? Only wishbone? | 10:20 |
| keesj | I don't know | 10:20 |
| olofk | I did a similar thing for litesata a couple of years ago and ended up just exposing the raw config regs and creating a bus adapter outside of the core | 10:21 |
| olofk | So, that's one issue. Then I can't figure out how the CDC works. There's a SDClockerS7() instance created but I don't understand how it's connected to the litesdcard core | 10:23 |
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| olofk | Another more general Litex question is about platform.request() | 10:38 |
| olofk | When I request the same resource twice, Python claims it doesn't exist anymore. Am I only supposed to request it once or is this a bug? | 10:38 |
| olofk | I also feel I lack a deep understanding of how the stream.Endpoint() class is supposed to be used | 10:57 |
| keesj | indeed the request is supposed to happen only once indeed | 10:57 |
| olofk | Cool. That explains things | 10:59 |
| keesj | (and https://github.com/enjoy-digital/litesdcard/blob/master/test/test_sdcard.py ) is pretty nice in showing the code works without a cpu core (e.e. just using the uar wishbone bridge) | 11:00 |
| tpb | Title: litesdcard/test_sdcard.py at master · enjoy-digital/litesdcard · GitHub (at github.com) | 11:00 |
| keesj | but the code is full of "autoCSR" and other magic stuff that works well in the context of migen but I don't know how well it is suitable for generating something like a sdcard core that can be reused. | 11:02 |
| olofk | But that code is just the part running on the PC side, right? | 11:03 |
| keesj | the test_sdcard.py is yes | 11:03 |
| olofk | And the stuff in examples is the corresponding FPGA side? | 11:04 |
| keesj | but not the core. e.g. https://github.com/enjoy-digital/litesdcard/blob/master/litesdcard/core.py#L28 | 11:04 |
| tpb | Title: litesdcard/core.py at master · enjoy-digital/litesdcard · GitHub (at github.com) | 11:04 |
| olofk | I'm trying to modify the arty exemple to be a bit more self-contained | 11:04 |
| keesj | yes ,pehrpas just call it with the correct arguments and see what the verilog looks like | 11:05 |
| olofk | This is what I have come up with so far https://gist.github.com/olofk/f121e9c0acdae17bb3167d3d75f81a31 | 11:09 |
| tpb | Title: nexys.py · GitHub (at gist.github.com) | 11:09 |
| olofk | But I have no idea why I get errors when I uncomment line 117 | 11:09 |
| olofk | AFAIK that signal should be part of the Endpoint struct | 11:09 |
| olofk | Hm.. payload.data works. Not sure I understand completely, but close enough :) | 11:13 |
| keesj | my strategy (in learning migen/litex) is really grep -rsi | 11:15 |
| keesj | e.g. finding examples | 11:16 |
| olofk | Yeah, mine too | 11:16 |
| olofk | In this case I picked it up from the verilog though :) | 11:17 |
| olofk | ok, so now I need to figure out how to expose the CSRs and what the hell I should write to them to make it start | 11:21 |
| olofk | I presume exposing a wb/axi slave interface would be the best way forward but I have no idea how to proceed with that | 11:37 |
| olofk | Anyone wants to do a Migen/Litex tutorial at ORConf? :) | 11:37 |
| olofk | Haha. This one contained most of my issues :) https://github.com/timvideos/litex-buildenv/wiki/Notes-and-Tips | 11:54 |
| tpb | Title: Notes and Tips · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 11:54 |
| _florent_ | olofk: you can use platform.lookup_request to get a signal you already requested | 12:29 |
| _florent_ | olofk: otherwise, for your SoC, i think what you want to do is remove the CPU from the example design | 12:29 |
| _florent_ | then maybe the best is to disable the CPU in the example design(cpu_type=None), then expose the wishbone. This way you will still be able to access the CSR through the wishbone. | 12:31 |
| _florent_ | SDClockerS7 i used to generate the SD clock and adapt frequency | 12:32 |
| olofk | Hi _florent_: I think I got something now. I'm probably doing things in weird ways though, so happy to hear some comments | 12:35 |
| olofk | I put it here https://gist.github.com/olofk/f121e9c0acdae17bb3167d3d75f81a31 | 12:35 |
| tpb | Title: nexys.py · GitHub (at gist.github.com) | 12:35 |
| olofk | I presumed that SDClockerS7 was the adaptive clock, but I can't figure out how clock domains work. How do you assign logic to different domains? | 12:36 |
| _florent_ | we use ClockDomainsRenamer to change the a clock of Module | 12:41 |
| _florent_ | it should be used in LiteSDCard with the clock created by SDClockerS7 | 12:41 |
| _florent_ | the possible issue i see with your core is that i don't think CSRs will be created collected since you are creating a Module and not a SoC. If you start from example, it will be the case. You also generate the csr map to .csv or .json (csr_csv or csr_json argument of Builder) | 12:48 |
| olofk | In the generated verilog it looks like the CSRs get assigned to unique addresses | 12:49 |
| olofk | But should I subclass BaseSoc instead? | 12:49 |
| olofk | SoCCore | 12:50 |
| _florent_ | using module could work, but reusing SoCCore will probably be easier to start with, but if you see that CSR are connected and are able to get the addresses of registers, you can continue with your code | 12:54 |
| _florent_ | sorry, i was just passing by, need to go | 12:54 |
| olofk | cool. I''ll test SoCCore at some point. Exporting the csrs would be nice | 12:54 |
| olofk | Thanks. Take care | 12:55 |
| olofk | Considering to package the sd emulator as a separate fusesoc core. Can anyone tell me a bit about the provenience of the code. Would be nice to have a single upstream repo instead of this trail of forks. Is it coming from scanlime's flipsyfat who in turn got it from ProjectVault? Did I miss any links? | 13:29 |
| olofk | Looks like the version in litesdcard is just a whitespace cleanup of flipsyfat | 13:34 |
| olofk | Oh well. More work to be done tomorrow | 13:34 |
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| keesj | hmm working on a sd emulator? | 14:20 |
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| mithro | _florent_: I would like to get litex-buildenv into a shape that your happy to use it :-) | 16:06 |
| _florent_ | mithro: to setup the environment, i really liked using lx-buildenv script from xobs when testing fomu | 18:57 |
| mithro | _florent_: When you get a chance, can you review https://github.com/litex-hub/linux-on-litex-vexriscv/pull/39/files ? | 19:03 |
| tpb | Title: soc_linux: adds support for I2CMaster by mateusz-holenko · Pull Request #39 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 19:03 |
| _florent_ | mithro: done and merged | 19:12 |
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