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| carlatwin | (LX P=arty C=mor1kx) juser@DESKTOP-KOJ4LVF:~/lhub/litex-buildenv$ uname -a | 00:48 |
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| carlatwin | Linux DESKTOP-KOJ4LVF 4.4.0-17763-Microsoft #379-Microsoft Wed Mar 06 19:16:00 PST 2019 x86_64 GNU/Linux | 00:48 |
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| xobs | What's the best way to mux io pins in litex? I'm looking to interleve a hardware SPI block with `spi_flash`, and it seems like that's almost doable. | 05:52 |
| xobs | The problem being that the SPI pins are bidirectional. In SpiFlashDualQuad they use a TSTriple. Is there something that exists that fakes that to let me mux it? | 05:53 |
| keesj | hmmm | 06:56 |
| keesj | I don't understand the faking part. | 06:57 |
| xobs | I guess what I'm looking to do is hand SpiFlash a "Pad-ish" object that it could pass to TSTriple, but that I could disconnect and hand over to a different block instead. | 06:58 |
| xobs | In a CPU, you can usually mux one pin between behaviors and the blocks themselves don't care about what's going on in the outside world. | 06:59 |
| keesj | I think... I am currently also working on something with bidirectinal pins and I copied code from litedram 's code base | 07:00 |
| keesj | this uses the special block. I think you are looking for an abtraction of a bidirectional pin | 07:00 |
| xobs | Yeah, one option is to redo it so that it accepts an "in", "out" and "oe" pins instead of a "Pad". | 07:01 |
| xobs | I'm wondering if such a thing exists already. | 07:02 |
| keesj | I am seraching .. I had something like that yesterday | 07:03 |
| xobs | Though, maybe it makes sense to change the SpiFlash() constructor to accept a Module that could be overriden for fancier bitbanging. | 07:03 |
| keesj | by itself this is already supported in verilog (setting the port to high impedence) ( https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/spi_flash.py indeed uses TSTriple) | 07:10 |
| tpb | Title: litex/spi_flash.py at master · enjoy-digital/litex · GitHub (at github.com) | 07:10 |
| keesj | is https://github.com/m-labs/migen/blob/master/migen/fhdl/specials.py#L52 Tristate note enough? | 07:10 |
| tpb | Title: migen/specials.py at master · m-labs/migen · GitHub (at github.com) | 07:10 |
| keesj | I am used to grepping code but for language type constructs I think a good reference manual would certainly help | 07:11 |
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| _florent_ | xobs: there is no pre-existing module to do that | 07:40 |
| _florent_ | but if you define pads like this: pads = Record([("clk", 1), ("cs_n", 1), ("dq_o", 4), ("dq_i", 4), ("dq_oe", 1)]) | 07:41 |
| _florent_ | and then in SPIFlash, so something like this: | 07:41 |
| _florent_ | https://www.irccloud.com/pastebin/xoImrr0n/ | 07:41 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 07:41 |
| _florent_ | sorry, like this: | 07:42 |
| _florent_ | https://www.irccloud.com/pastebin/UpzsO4fn/ | 07:42 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 07:42 |
| _florent_ | then you will be able to put the TSTriple outside | 07:42 |
| xobs | _florent_: that looks like an interesting (and clever) approach, thanks! | 07:43 |
| _florent_ | but the actual SPIFlash is indeed not easy to modify, i'd like we make it more generic and easy to modify | 07:43 |
| _florent_ | your idea about having a specific module for the bitbang logic and pass it as a parameter was also interesting and could ease readibility | 07:48 |
| _florent_ | in fact maybe we should remove the bitbang logic from SpiFlashDualQuad/SpiFlashSingle | 07:48 |
| _florent_ | create SpiFlashDualQuadBitbang/SpiFlashSingleBitbang modules | 07:49 |
| xobs | That's what I'm thinking. Or something similar. | 07:49 |
| xobs | Right now I'm looking into what it would take to use the SB_SPI block. | 07:50 |
| xobs | It has an initialization process, where 5 registers must be configured at boot. Is there anything like that in litex? | 07:50 |
| _florent_ | and just create a mux with the modified pads record in SpiFlash when bitbang is needed | 07:50 |
| xobs | Something where, at reset, it steps through address/data pairs and writes them to registers, and continues when an "ACK" line is asserted. | 07:51 |
| _florent_ | no sorry, i haven't used SB_SPI yet and not aware others project using it (with litex) | 07:51 |
| xobs | Okay, I'll just use a FSM to load the registers. Thanks! | 07:52 |
| xobs | _florent_: do you have an example of indexing an array in the synthesized output? I have an array "init_dat = [0, 1, 0x80, 0x80, 12, 0xff]" and I'd like to access it from the design, but of course you can't index Python arrays with Signals. | 08:39 |
| xobs | I could create a Memory or similar, and manually manage it, but I feel like this must have a ready-made solution. | 08:39 |
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| _florent_ | xobs: sorry was away | 10:21 |
| _florent_ | you can use Migen's Arrays | 10:21 |
| _florent_ | https://github.com/m-labs/migen/blob/master/examples/basic/arrays.py | 10:22 |
| tpb | Title: migen/arrays.py at master · m-labs/migen · GitHub (at github.com) | 10:22 |
| _florent_ | something like this: init_dat = Array(Signal(8, reset=dat) for dat in [0, 1, 0x80, 0x80, 12, 0xff])) | 10:23 |
| xobs | florent: thanks! That looks like just what I need. | 11:55 |
| xobs | Right now it's much less elegant. For example: https://github.com/im-tomu/valentyusb/blob/master/valentyusb/usbcore/cpu/dummyusb.py#L38 | 11:55 |
| tpb | Title: valentyusb/dummyusb.py at master · im-tomu/valentyusb · GitHub (at github.com) | 11:55 |
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| futarisIRCcloud | https://abopen.com/news/openpitons-juxtapiton-processor-to-get-open-source-i486-core/ | 21:11 |
| tpb | Title: OpenPitons JuxtaPiton Processor to get Open-Source i486 Core - AB Open (at abopen.com) | 21:11 |
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