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| futarisIRCcloud | https://orconf.org/ - Bordeaux, France - September, 27th to 29th, 2019 | 00:42 |
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| tpb | Title: ORConf 2019 (at orconf.org) | 00:42 |
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| keesj | nice | 07:49 |
| tweakoz | @ _florent_ : is there a reason not to have an assert like this: (line 202 in the post) https://github.com/tweakoz/litex/commit/de9b36a4b0a41296fa0bc3053d977751342cd807#diff-6ab5fc4a5a670ad0348e63df102c7148R202 | 08:17 |
| tpb | Title: Update csr_bus.py · tweakoz/litex@de9b36a · GitHub (at github.com) | 08:17 |
| tweakoz | I switched to a CSR like you said up above to get my re signal. it did not work correctly due to the CSR in question being 32 bits. 32 bit CSR's allocated 4 slots of the address decoder space, but they only incremented i by 1 in the CSRBank "for i, c in enumerate(self.simple_csrs):" loop. this caused a csr select failure. | 08:24 |
| tweakoz | so the assert I added would have caught that. Though maybe I should try incrementing i by c.size and see if that works also. | 08:26 |
| tweakoz | Im guessing incrementing by c.size wouldn't work due to bus size. duh.. | 08:45 |
| tweakoz | I'd rather do 32 bit bus size anyway. I think it was the SDRAM system preventing it... | 08:46 |
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| _florent_ | tweakoz: i'll have a look, but yes we should probably add an assert when using CSR (vs CSRStorage/CSRStatus that can be > bus.data_width) | 09:59 |
| _florent_ | tweakoz: the SDRAM calibration logic does not handle csr_data_width of 32, it should be rewritten to be more generic, so yes, if you use SDRAM, you have to use csr_data_width = 8 | 10:00 |
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