Monday, 2019-07-01

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tweakozI need a little migen/litex help. I cannot figure out how to get my CPU->FIFO->FIFO->CPU (on linux) test working.00:33
tweakozmy soc definition is here: https://github.com/tweakoz/litex-testsoc/blob/issue-fifo-irq/soc/modules/top.py#L12100:33
tpbTitle: litex-testsoc/top.py at issue-fifo-irq · tweakoz/litex-testsoc · GitHub (at github.com)00:33
tweakozthe results I am seeing are here: https://github.com/tweakoz/litex-testsoc/blob/issue-fifo-irq/testapp/runlog.md00:33
tpbTitle: litex-testsoc/runlog.md at issue-fifo-irq · tweakoz/litex-testsoc · GitHub (at github.com)00:33
tweakozI am admittedly a litex/migen newb still.00:34
tweakozthe source code used to generate the results is here: https://github.com/tweakoz/litex-testsoc/blob/issue-fifo-irq/testapp/main.cpp#L23000:37
tpbTitle: litex-testsoc/main.cpp at issue-fifo-irq · tweakoz/litex-testsoc · GitHub (at github.com)00:37
tweakozAny help would be mucho appreciated.00:39
tweakozdoh went through all the work of prepping the example for review, and in the processed noticed I forgot to add inp_fifo to the soc's submodule list. doh.00:41
tweakozok first issue solved, inp-fifo gets data. (it was the missing submodule add).00:58
tweakozsecond problem. I cannot figure out how to notify the fifo that the cpu has read (popped) an item of the fifo. I dont have interrupts, So I cannot do what the uart does (If I read the source correctly, uart uses an interrupt clear event to signal the read ack)01:00
tweakozsee: https://github.com/tweakoz/litex-testsoc/blob/issue-fifo-irq/testapp/runlog2.md01:00
tpbTitle: litex-testsoc/runlog2.md at issue-fifo-irq · tweakoz/litex-testsoc · GitHub (at github.com)01:00
tweakozand: https://github.com/tweakoz/litex-testsoc/blob/issue-fifo-irq/soc/modules/top.py#L16901:01
tpbTitle: litex-testsoc/top.py at issue-fifo-irq · tweakoz/litex-testsoc · GitHub (at github.com)01:01
tweakozIs there a way to get a csr read transaction to emit a 1 cycle long "read occurred" signal - I think I could use that to signal the read ack for the fifo.01:03
tweakoz?01:03
futarisIRCcloudhttps://www.crowdsupply.com/xips-technology/fireant03:21
tpbTitle: FireAnt | Crowd Supply (at www.crowdsupply.com)03:21
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RedMercurythey say publish and be damned, so i made some verilator and spinalhdl rules for the bazel build system: https://github.com/redmercury/rules_hdl05:55
tpbTitle: GitHub - redmercury/rules_hdl: Various bazel rules for verilator and SpinalHDL. (at github.com)05:55
_florent_tweakoz: to read your fifo, you can use a CSR() and use the re signal07:35
_florent_re will be set for 1 cycle when you will do a write/read to this register07:36
_florent_ex: in litescope, i'm using a mem_ready CSR; https://github.com/enjoy-digital/litescope/blob/master/litescope/core.py#L15007:36
tpbTitle: litescope/core.py at master · enjoy-digital/litescope · GitHub (at github.com)07:36
_florent_and using .re to ack one data: https://github.com/enjoy-digital/litescope/blob/master/litescope/core.py#L22607:37
tpbTitle: litescope/core.py at master · enjoy-digital/litescope · GitHub (at github.com)07:37
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somlodaveshah: problem was NOT caused by commit a0d3d2bb20:06
somloreverting that on top of yosys dd8d264 didn't fix the DOA bitstream issue...20:07
daveshahsomlo: thanks for testing20:07
somloso much for the low hanging fruit... I need to leave the office, and won't have access to my fpga till tomorrow20:07
somlobut if you want to test, try https://github.com/gsomlo/yoloRISC20:08
tpbTitle: GitHub - gsomlo/yoloRISC: A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga (at github.com)20:08
somloworks as of yosys #c90789920:08
daveshahThanks, I'll have a look if I have time20:08
somlogot it up to 55 MHZ with latest trellis and nextpnr, which is awesome in its own right :)20:09
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