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| tweakoz | I need a little migen/litex help. I cannot figure out how to get my CPU->FIFO->FIFO->CPU (on linux) test working. | 00:33 |
|---|---|---|
| tweakoz | my soc definition is here: https://github.com/tweakoz/litex-testsoc/blob/issue-fifo-irq/soc/modules/top.py#L121 | 00:33 |
| tpb | Title: litex-testsoc/top.py at issue-fifo-irq · tweakoz/litex-testsoc · GitHub (at github.com) | 00:33 |
| tweakoz | the results I am seeing are here: https://github.com/tweakoz/litex-testsoc/blob/issue-fifo-irq/testapp/runlog.md | 00:33 |
| tpb | Title: litex-testsoc/runlog.md at issue-fifo-irq · tweakoz/litex-testsoc · GitHub (at github.com) | 00:33 |
| tweakoz | I am admittedly a litex/migen newb still. | 00:34 |
| tweakoz | the source code used to generate the results is here: https://github.com/tweakoz/litex-testsoc/blob/issue-fifo-irq/testapp/main.cpp#L230 | 00:37 |
| tpb | Title: litex-testsoc/main.cpp at issue-fifo-irq · tweakoz/litex-testsoc · GitHub (at github.com) | 00:37 |
| tweakoz | Any help would be mucho appreciated. | 00:39 |
| tweakoz | doh went through all the work of prepping the example for review, and in the processed noticed I forgot to add inp_fifo to the soc's submodule list. doh. | 00:41 |
| tweakoz | ok first issue solved, inp-fifo gets data. (it was the missing submodule add). | 00:58 |
| tweakoz | second problem. I cannot figure out how to notify the fifo that the cpu has read (popped) an item of the fifo. I dont have interrupts, So I cannot do what the uart does (If I read the source correctly, uart uses an interrupt clear event to signal the read ack) | 01:00 |
| tweakoz | see: https://github.com/tweakoz/litex-testsoc/blob/issue-fifo-irq/testapp/runlog2.md | 01:00 |
| tpb | Title: litex-testsoc/runlog2.md at issue-fifo-irq · tweakoz/litex-testsoc · GitHub (at github.com) | 01:00 |
| tweakoz | and: https://github.com/tweakoz/litex-testsoc/blob/issue-fifo-irq/soc/modules/top.py#L169 | 01:01 |
| tpb | Title: litex-testsoc/top.py at issue-fifo-irq · tweakoz/litex-testsoc · GitHub (at github.com) | 01:01 |
| tweakoz | Is there a way to get a csr read transaction to emit a 1 cycle long "read occurred" signal - I think I could use that to signal the read ack for the fifo. | 01:03 |
| tweakoz | ? | 01:03 |
| futarisIRCcloud | https://www.crowdsupply.com/xips-technology/fireant | 03:21 |
| tpb | Title: FireAnt | Crowd Supply (at www.crowdsupply.com) | 03:21 |
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| RedMercury | they say publish and be damned, so i made some verilator and spinalhdl rules for the bazel build system: https://github.com/redmercury/rules_hdl | 05:55 |
| tpb | Title: GitHub - redmercury/rules_hdl: Various bazel rules for verilator and SpinalHDL. (at github.com) | 05:55 |
| _florent_ | tweakoz: to read your fifo, you can use a CSR() and use the re signal | 07:35 |
| _florent_ | re will be set for 1 cycle when you will do a write/read to this register | 07:36 |
| _florent_ | ex: in litescope, i'm using a mem_ready CSR; https://github.com/enjoy-digital/litescope/blob/master/litescope/core.py#L150 | 07:36 |
| tpb | Title: litescope/core.py at master · enjoy-digital/litescope · GitHub (at github.com) | 07:36 |
| _florent_ | and using .re to ack one data: https://github.com/enjoy-digital/litescope/blob/master/litescope/core.py#L226 | 07:37 |
| tpb | Title: litescope/core.py at master · enjoy-digital/litescope · GitHub (at github.com) | 07:37 |
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| somlo | daveshah: problem was NOT caused by commit a0d3d2bb | 20:06 |
| somlo | reverting that on top of yosys dd8d264 didn't fix the DOA bitstream issue... | 20:07 |
| daveshah | somlo: thanks for testing | 20:07 |
| somlo | so much for the low hanging fruit... I need to leave the office, and won't have access to my fpga till tomorrow | 20:07 |
| somlo | but if you want to test, try https://github.com/gsomlo/yoloRISC | 20:08 |
| tpb | Title: GitHub - gsomlo/yoloRISC: A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga (at github.com) | 20:08 |
| somlo | works as of yosys #c907899 | 20:08 |
| daveshah | Thanks, I'll have a look if I have time | 20:08 |
| somlo | got it up to 55 MHZ with latest trellis and nextpnr, which is awesome in its own right :) | 20:09 |
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