| *** tpb has joined #litex | 00:00 | |
| *** tweakoz has joined #litex | 03:13 | |
| *** rohitksingh_work has joined #litex | 05:14 | |
| _florent_ | Dolu: nice for the ATWILC1000, not sure we are currently a lot faster with the onboard ethernet PHYs :) | 05:43 |
|---|---|---|
| *** sorear_ has joined #litex | 06:16 | |
| *** sorear has quit IRC | 06:24 | |
| *** Dolu has quit IRC | 06:28 | |
| *** Dolu has joined #litex | 06:29 | |
| *** sorear_ is now known as sorear | 06:29 | |
| *** tweakoz has quit IRC | 08:10 | |
| keesj_ | is there a nice way to combine the wishbone uart interface and the serial? | 08:17 |
| keesj_ | like.. makeking litex_term read/.write an in memory buffer (over the wishbone uart interface) | 08:18 |
| *** rohitksingh_work has quit IRC | 09:59 | |
| *** rohitksingh_work has joined #litex | 10:01 | |
| *** Dolu1990 has joined #litex | 10:03 | |
| *** rohitksingh_work has quit IRC | 10:44 | |
| *** rohitksingh_work has joined #litex | 10:45 | |
| *** Dolu1990 has quit IRC | 11:13 | |
| _florent_ | keesj_: you can use the UART wishbone bridge for that | 12:08 |
| _florent_ | keesj_: since it gives you access to the wishbone, if you attach a memory to the wishbone, you'll be able to access it over UART | 12:09 |
| keesj_ | but.. I want to combine it witha core with also uses the uart | 12:26 |
| keesj_ | Also I am playing with the AutoCSR at the moment and would like to read out a signal (32 bits wide). Should I be able to assing the storage to the signal in a sync block? | 12:29 |
| keesj_ | or perhaps even self.readc.storage = self.read_counter ? | 12:29 |
| *** rohitksingh_work has quit IRC | 13:19 | |
| _florent_ | keesj_: with the bios, you can write or read memory with mw/mr command | 13:41 |
| _florent_ | so you could add a script on top of litex_term to do that, but that will be a bit slow | 13:41 |
| _florent_ | for the csr, you can do, self.sync += self.readc.storage.eq(self.read_counter) | 13:42 |
| _florent_ | you can assign CSR signals as you would do for others signals | 13:43 |
| keesj_ | RROR: [Synth 8-2576] procedural assignment to a non-register readc_storage is not permitted [/home/why/projects/ddr3/litex/exset/10_trace_ddr_state/build/top.v:1435] | 13:49 |
| keesj_ | (using CSRStorage and Signal) https://pastebin.com/rvzvEQEG | 13:50 |
| tpb | Title: class DDRStateCounter(Module,AutoCSR): def __init__(self,ddrstate4): - Pastebin.com (at pastebin.com) | 13:50 |
| keesj_ | wire [31:0] readc_storage; | 14:31 |
| keesj_ | e.g. readc_storage is defined as a wire not a register | 14:31 |
| keesj_ | in most examples I see the logic is kinda reversed e.g. CSR storage is assigned to a different signal (and CSRSatus has a status that I can probably write to) | 14:35 |
| _florent_ | keesj_: ah yes sorry, you should use a CSRStatus for that no? | 17:35 |
| keesj_ | CSRStatus indeed worked. still from the documentation it looks like CSRStorage is a read / write register | 17:50 |
| *** flammit has joined #litex | 18:13 | |
| _florent_ | you can read a CSRStorage, it will return the value that was written to it. You can also use write_from_dev on a CSRStorage, but it's only needed on very specific cases, otherwise, i would recommend splitting in CSRStorage/CSRStatus | 19:32 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!