Saturday, 2019-06-22

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Dolu1Currently looking to add unaligned access support in the emulator, have it required for the ATWILC1000 in access point mode.12:28
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sorearhttps://sourceware.org/ml/libc-alpha/2019-06/msg00534.html riscv32 glibc upstreaming started :D16:50
tpbTitle: Alistair Francis - [RFC v1 00/16] RISC-V glibc port for the 32-bit (at sourceware.org)16:50
daveshahsorear: very nice17:18
daveshahThanks for spotting that!17:18
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Dolu1Also had issues with missing libatomic.so.1: ?19:34
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mnrHello, I'm a newbie to litex and I've started experimenting around with https://github.com/litex-hub/linux-on-litex-vexriscv. When using the prebuilt binaries from https://github.com/enjoy-digital/linux-on-litex-vexriscv-prebuilt, I can successfully run the simulation with ./sim.py. When trying to build everything myself, I'm somewhat stuck at how emulator/emulator.bin is intended to be built.20:16
mnremulator/Makefile refers to $(SOC_DIRECTORY), but I see nothing that would define this variable and AFAICS the README.md doesn't provide any information about that. Pointers welcome :).20:16
mnrHm, looks like the last line was too long and got truncated, therefore the second part again:20:26
mnremulator/Makefile refers to $(SOC_DIRECTORY), but I see nothing that would define this variable and AFAICS the README.md doesn't provide any information about that. Pointers welcome :).20:26
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futarisIRCcloudCool. Alistair seems to be pushing a bunch of 32 bit RISC-V stuff along. Would have been nice to chat with Alistair in person. I met Palmer two days ago in person at the Sydney RISC-V Tech Symposium.21:05
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futarisIRCcloudmnr: Sorry, the README.md hasn't been updated for the buildroot BR2_EXTERNAL change. https://github.com/litex-hub/linux-on-litex-vexriscv/issues/2121:07
tpbTitle: use BR2_EXTERNAL buildroot feature · Issue #21 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)21:07
futarisIRCcloudmnr: Actually the commits for that change, already reference how to build the filesystem correctly.21:14
futarisIRCcloudmnr: didn't see that you wanted to build the emulator/emulator.bin ..21:16
futarisIRCcloudIt should be where your local litex install is.21:19
futarisIRCcloudhttps://github.com/enjoy-digital/litex/tree/master/litex/soc/software21:19
tpbTitle: litex/litex/soc/software at master · enjoy-digital/litex · GitHub (at github.com)21:19
mnrfutarisIRCcloud: Thanks a lot. I still appear to miss something in the big picture: I have successfully run " ./make.py --board=versa_ecp5 --build", which has built a bitstream, but doesn't seem to build the bits necessary for running the simulation. What is intended to call emulator/Makefile with the correct variables?21:39
mnrI'm completely new to the litex build system, so sorry if I'm missing something obvious.21:40
mithroWow, spi flash is complicated....21:41
mnremulator/Makefile defines "BUILD_DIR=../build/" and then references "$(BUILD_DIR)/software/include/generated/variables.mak", but that doesn't exist because there is a target-specific directory "versa_ecp5" below ../build.21:43
mnrThe latter then has software/include/generated/variables.mak below it.21:44
futarisIRCcloudTry copying the files from linux-on-litex-vexriscv-prebuilt ...21:47
mnrfutarisIRCcloud: Doing that gives my a working simulation with ./sim.py; what I'm trying to understand is what I need to do to build all bits from a fresh checkout. I know how to build the kernel and the rootfs with buildroot, but the emulator binary is still a mystery to me.21:49
mnrIs ./make.py supposed to create everything required for running ./sim.py or not?21:52
futarisIRCcloudI think it was documented in this issue (  https://github.com/SpinalHDL/VexRiscv/issues/60#bottom ). We probably should update README.md in this repo.21:53
tpbTitle: Linux on VexRiscv · Issue #60 · SpinalHDL/VexRiscv · GitHub (at github.com)21:53
futarisIRCcloudI'm on mobile, so I don't quite recall at the moment.21:53
daveshahmithro: have you found SPI NAND yet?21:55
futarisIRCcloudhttps://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/make.py22:00
tpbTitle: linux-on-litex-vexriscv/make.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)22:00
mithrodaveshah: nope22:06
daveshahmithro: e.g. https://www.digikey.co.uk/product-detail/en/winbond-electronics/W25N01GVZEIG-TR/W25N01GVZEIGCT-ND/739354522:10
tpbTitle: W25N01GVZEIG TR Winbond Electronics | Integrated Circuits (ICs) | DigiKey (at www.digikey.co.uk)22:11
daveshahVarious extra fun like bad block management22:11
mnrfutarisIRCcloud: "./make.py --board=versa_ecp5 --build" happily builds an FPGA bitstream for me, but it doesn't build everything required for running a simulation with ./sim.py. The latter fails because it cannot load "emulator/emulator.bin" which hasn't been built by make.py. A build log is available at https://paste.debian.net/hidden/bde9f0e0/ .22:21
tpbTitle: Debian Pastezone (at paste.debian.net)22:21
mnrfutarisIRCcloud: So obviously I'm missing some step, but I don't know which one, as the README.md doesn't mention anything in this regard.22:22
futarisIRCcloudI think soc_linux might build the directory you are after.22:43
futarisIRCcloudhttps://github.com/litex-hub/linux-on-litex-vexriscv/commits/master/soc_linux.py22:44
tpbTitle: History for soc_linux.py - litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)22:44
futarisIRCcloudBest to ask _florent_ in 10 hours or so.22:44
mnrfutarisIRCcloud: ok, will do. thanks a lot for your help.22:49
_florent_mnr: there is a step missing indeed, i'll fix that, but to build emulator.bin, you can run ./sim.py (that will fails), cd emulator, make, cd .., ./sim.py22:51
mnr_florent_: That unfortunately doesn't work for me. Log at https://paste.debian.net/hidden/c1d5f932/23:02
tpbTitle: Debian Pastezone (at paste.debian.net)23:02
mnr_florent_: The make failure happes because the Makefile variables used by emulator/Makefile aren't set appropriately, but I don't know what part of the build system is supposed to set them.23:04

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